Hashing functions play a fundamental role in modern cryptography. Such functions process data of finite length and produce a small fixed size output referred to as a digest or hash. Typical applications of these functions include data integrity verification and message authentication schemes.
Among the most widely-used cryptographic hash functions today are Message Digest 5 (MD5) and the Secure Hash Algorithm family (SHA-0, SHA-1, and SHA-2). In recent years many attacks against these functions, excluding SHA-2, have been published thereby compromising their security. The security of Whirlpool, a recently introduced hashing function, has yet to be compromised.
As a result of the weaknesses found the National Institute of Standards and Technology (NIST) has solicited submissions for new and more secure algorithms to replace the ones currently compromised. PHASH is one such algorithm proposed to NIST.
The MD5 and SHA family of hash functions can be described as iterative. The main difference between PHASH and such functions is that PHASH can be executed in parallel.
The proposed thesis will compare and contrast hardware implementations of SHA-512, Whirlpool and PHASH targeted for the Virtex-4 XC4VFX60 FPGA. VHDL will be used to obtain behavioral and synthesizable models for the three algorithms. The synthesized architectures will then be programmed onto the FPGA to verify the correct operation of the designs.