Cryptographic hash functions play a fundamental role in modern cryptography. Such functions take as input data of finite length and produce a small fixed size output, typically referred to as a hash-value or hash. Typical applications of these functions include data integrity verification as well as message authentication schemes.
One of the most widely-used cryptographic hash functions today is the Secure Hash Algorithm family (SHA-0, SHA-1, and SHA-2). A fairly new hashing function called Whirlpool has been getting more attention as it offers several benefits over the Secure Hash Algorithm family.
With the ever increasing amounts of data that needs to be hashed the throughput of hashing functions becomes an important factor. FPGAs are often used in hardware implementations that require high throughput. This paper presents a simple SHA-512 implementation as well as several Whirlpool implementations targeted for the XC4VFX60 FPGA. All implementations use techniques that have been previously proposed in literature.
The SHA-512 implementation requires 2073 CLB slices and achieves a throughput over 1.3 Gbps and the Whirlpool implementation which does not use any Block RAM requires 6178 CLB slices and achieves a throughput over 6.1 Gbps. The SHA-512 implementation is comparable to the currently published implementations. The presented Whirlpool implementation requires 18% less CLB slices and achieves a 30% increase in throughput over a comparable implementation presented in literature.
-----------------------------------------------
Cryptographic hash functions play a fundamental role in modern cryptography. Such functions take as input data of finite length and produce a small fixed size output, typically referred to as a hash-value or hash. Typical applications of these functions include data integrity verification as well as message authentication schemes.
One of the most widely-used cryptographic hash functions today is the Secure Hash Algorithm family (SHA-0, SHA-1, and SHA-2). A fairly new hashing function called Whirlpool has been getting more attention as it offers several benefits over the Secure Hash Algorithm family.
With the ever increasing amounts of data that needs to be hashed the throughput of hashing functions becomes an important factor. FPGAs are often used in hardware implementations that require high throughput. This paper presents a simple SHA-512 implementation as well as several Whirlpool implementations targeted for the XC4VFX60 FPGA. All implementations use techniques that have been previously proposed in literature.
The SHA-512 implementation requires 2073 CLB slices and achieves a throughput over 1.3 Gbps and the Whirlpool implementation which does not use any Block RAM requires 6178 CLB slices and achieves a throughput over 6.1 Gbps. The SHA-512 implementation is comparable to the currently published implementations. The presented Whirlpool implementation requires 18% less CLB slices and achieves a 30% increase in throughput over a comparable implementation presented in literature.