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#963518 ·published 2008-03-30 17:04 UTC
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root@Bellinha:~# modprobe b43

root@Bellinha:~# dmesg |tail -n 30
e100: eth0: e100_watchdog: link up, 100Mbps, full-duplex
ADDRCONF(NETDEV_CHANGE): eth0: link becomes ready
eth0: no IPv6 routers present
b43-phy0 debug: Removing Interface type 2
b43-phy0 debug: Wireless interface stopped
b43-phy0 debug: DMA-32 0x0200 (RX) max used slots: 7/64
b43-phy0 debug: DMA-32 0x02A0 (TX) max used slots: 0/128
b43-phy0 debug: DMA-32 0x0280 (TX) max used slots: 0/128
b43-phy0 debug: DMA-32 0x0260 (TX) max used slots: 0/128
b43-phy0 debug: DMA-32 0x0240 (TX) max used slots: 0/128
b43-phy0 debug: DMA-32 0x0220 (TX) max used slots: 22/128
b43-phy0 debug: DMA-32 0x0200 (TX) max used slots: 0/128
ACPI: PCI interrupt for device 0000:01:0a.0 disabled
ACPI: PCI Interrupt 0000:01:0a.0[A] -> Link [LNKD] -> GSI 11 (level, low) -> IRQ 11
ssb: Sonics Silicon Backplane found on PCI device 0000:01:0a.0
b43-phy0: Broadcom 4306 WLAN found
b43-phy0 debug: Found PHY: Analog 2, Type 2, Revision 2
b43-phy0 debug: Found Radio: Manuf 0x17F, Version 0x2050, Revision 2
b43-phy0 debug: DebugFS (CONFIG_DEBUG_FS) not enabled in kernel config
phy0: Selected rate control algorithm 'simple'
input: b43-phy0 as /devices/virtual/input/input7
b43-phy0 debug: Loading firmware version 351.126 (2006-07-29 05:54:02)
b43-phy0 debug: Chip initialized
b43-phy0 debug: 30-bit DMA initialized
Registered led device: b43-phy0:tx
Registered led device: b43-phy0:rx
Registered led device: b43-phy0:radio
b43-phy0 debug: Wireless interface started
b43-phy0 debug: Adding Interface type 2
ADDRCONF(NETDEV_UP): wlan0: link is not ready