rendered paste bodydiff -ur -x CVS src/arminsns.cpp haret-msm/src/arminsns.cpp
--- src/arminsns.cpp 2007-09-12 12:31:47.000000000 +0200
+++ haret-msm/src/arminsns.cpp 2008-03-18 08:17:23.000000000 +0100
@@ -113,6 +113,9 @@
Output("c%02d: %08x | c%02d: %08x"
, i, getSetCP(0, cp, 0, i, 0, 0, 0)
, i + 8, getSetCP(0, cp, 0, i + 8, 0, 0, 0));
+ for(int i=0;i<5;i++)
+ Output("c15, 0, c2, %d = %8x\n",i,getSetCP(0, 15, 15, 0, 2, i,0));
+
}
REG_DUMP(0, "CP", cpuDumpCP,
"CP <cp>\n"
diff -ur -x CVS src/cpu.cpp haret-msm/src/cpu.cpp
--- src/cpu.cpp 2008-01-13 00:10:17.000000000 +0100
+++ haret-msm/src/cpu.cpp 2008-03-14 00:30:27.000000000 +0100
@@ -204,6 +204,9 @@
static int controlCount;
+volatile unsigned *const VICEN0=(unsigned *)0xb4e00010;
+volatile unsigned *const VICEN1=(unsigned *)0xb4e00014;
+
// Take over CPU control from wince. After calling this, the
// application should not be interrupted by any interrupts or faults.
// In general, the code should not make any OS calls until after
@@ -214,7 +217,7 @@
if (controlCount++)
// Already in a critical section.
return;
-
+ Sleep(1000);
// Flush log to disk (in case we don't survive)
flushLogFile();
@@ -222,12 +225,16 @@
touchAppPages();
// Disable interrupts.
+
unsigned long temp;
__asm__ __volatile__(
"mrs %0, cpsr\n"
" orr %0, %0, #0xc0\n"
" msr cpsr_c, %0"
: "=r" (temp) : : "memory");
+ // disable VIC
+ // *VICEN0=0;
+ // *VICEN1=0;
}
// Return to normal processing.
Nur in haret-msm/src: cpu.cpp~.
diff -ur -x CVS src/fbwrite.cpp haret-msm/src/fbwrite.cpp
--- src/fbwrite.cpp 2008-03-16 02:13:43.000000000 +0100
+++ haret-msm/src/fbwrite.cpp 2008-03-10 02:21:51.000000000 +0100
@@ -81,7 +81,7 @@
char *d = &buf[sizeof(buf) - 1];
*d-- = '\0';
for (;;) {
- *d = (val % 10) + '0';
+ *d = val % 10;
val /= 10;
if (!val)
break;
@@ -115,6 +115,34 @@
fb_putsinglehex(fbi, (val >> 0) & 0xf);
}
+unsigned *const MSM_MDP_BASE=(unsigned *)0xb2100000;
+unsigned *const MDP_DMA_START=(unsigned *)(MSM_MDP_BASE + 0x10044);
+unsigned *const MDP_INTR_STATUS=(unsigned *)(MSM_MDP_BASE + 0x00024);
+unsigned *const MDP_INTR_CLEAR=(unsigned *)(MSM_MDP_BASE + 0x00028);
+unsigned *const MDP_VSYNC_CTRL=(unsigned *)(MSM_MDP_BASE + 0x0008c);
+unsigned *const MDP_DISPLAY0_START=(MSM_MDP_BASE + 0x00030);
+unsigned *const MDP_ADDRESS=(MSM_MDP_BASE + 0x10188);
+unsigned *const MDP_INTR_ENABLE=(MSM_MDP_BASE + 0x00020);
+
+/*
+void __preload display() {
+//unsigned oi=*MDP_INTR_ENABLE;
+while(*MDP_INTR_STATUS!=0);
+
+*MDP_INTR_ENABLE=0;
+*MDP_INTR_CLEAR=*MDP_INTR_STATUS;
+*MDP_INTR_STATUS=0;
+
+//*MDP_ADDRESS=0x700000;
+*MDP_VSYNC_CTRL=0;
+*MDP_DMA_START=0;
+//*MDP_DISPLAY0_START=0x1000;
+//while(*MDP_INTR_STATUS=0);
+*MDP_INTR_CLEAR=*MDP_INTR_STATUS;
+*MDP_INTR_STATUS=0;
+}
+*/
+
// Write a string to the framebuffer.
void __preload
fb_printf(fbinfo *fbi, const char *fmt, ...)
@@ -166,14 +194,19 @@
va_end(args);
}
+
+
// Clear the screen.
void
fb_clear(fbinfo *fbi)
{
+//for(int i=0;i<255;i++) {
if (!fbi->fb)
return;
memset(fbi->fb, 0, fbi->scrx * fbi->scry * BPP);
fbi->x = fbi->y = 0;
+// display();
+//}
}
// Initialize an fbi structure.
diff -ur -x CVS src/linboot.cpp haret-msm/src/linboot.cpp
--- src/linboot.cpp 2008-02-10 18:58:20.000000000 +0100
+++ haret-msm/src/linboot.cpp 2008-03-18 21:40:58.000000000 +0100
@@ -27,7 +27,7 @@
#include "resource.h"
// Kernel file name
-static char *bootKernel = "zimage";
+static char *bootKernel = "zImage";
// Initrd file name
static char *bootInitrd = "";
// Kernel command line
@@ -241,28 +241,112 @@
return IN_RANGE(pd->physFB, pd->startRam
, PHYSOFFSET_INITRD + pd->initrdSize);
}
+volatile unsigned *const LEDV=(unsigned *)0x92a00c00;
+volatile unsigned *const LEDP=(unsigned *)0xa9300c00;
+/*
+static int __preload wait(int n) {
+int f=0;
+for(int i=0;i<n;i++)
+ for(int k=0;k<(1<<7);k++)
+ for(int j=0;j<(1<<15);j++)
+ f=f+j+k+i;
+return f;
+}
+
+
+
+static void __preload flash(int n,int p) {
+return;
+unsigned const OFF=0x0800;
+unsigned const ON=0x1800;
+volatile unsigned *led;
+if(p) led=LEDP; else led=LEDV;
+*led=OFF;
+wait(5);
+for(int i=0;i<n;i++) {
+ wait(1);
+ *led=ON;
+ wait(1);
+ *led=OFF;
+ wait(1);
+}
+wait(5);
+}
+*/
+#define FLASH(n) for(unsigned i=0;i<(1<<19);i++) *LEDP=0x0800;\
+for(int j=0;j<n;j++) {\
+ for(unsigned i=0;i<(1<<18);i++) *LEDP=0x1800;\
+ for(unsigned i=0;i<(1<<18);i++) *LEDP=0x0800;\
+}\
+for(unsigned i=0;i<(1<<19);i++) *LEDP=0x0800;
+
+
+#define LEDOFF for(unsigned i=0;i<(1<<21);i++) *LEDV=0x0800;
// Code to launch kernel.
static void __preload
preloader(struct preloadData *data)
{
- data->fbi.fb = (uint16 *)data->physFB;
- data->fbi.fonts = (unsigned char *)data->physFonts;
+// while(1) *LEDV=0x1800;
+// flash(4,0);
+//FLASH(3)
+ /*
+ asm("mov %0,#0xaa000000\n"\
+ "add %0,#0x200000\n"\
+ "add %0,#0xb\n"\
+ "mcr p15, 0, %0, c15, c2, 4\n"\
+ : : "r"(0));
+ volatile unsigned *const MDP_BASE=(unsigned *)0xaa200000;
+ volatile unsigned *const BYPASS33=MDP_BASE+0x10184/4;
+ volatile unsigned *const BYPASS34=MDP_BASE+0x10188/4;
+ volatile unsigned *const BYPASS35=MDP_BASE+0x1018c/4;
+ volatile unsigned *const BYPASS37=MDP_BASE+0x10194/4;
+ volatile unsigned *const BYPASS40=MDP_BASE+0x101a0/4;
+ volatile unsigned *const BYPASS41=MDP_BASE+0x101a4/4;
+ volatile unsigned *const DMACONFIG=MDP_BASE+0x10180/4;
+ volatile unsigned *const VSYNC=MDP_BASE+0x0008c/4;
+ volatile unsigned *const DMASTART=MDP_BASE+0x10044/4;
+
+ volatile unsigned *const INTSTATUS=MDP_BASE+0x00024/4;
+ volatile unsigned *const INTCLEAR=MDP_BASE+0x00028/4;
+ unsigned FB=0x00700000;
+ while(1) {
+ while(*INTSTATUS&4);
+ *INTCLEAR=*INTSTATUS&4;
+ *BYPASS33=0x014000f0;
+ *BYPASS34=FB;
+ *BYPASS35=0x000001e0;
+ *BYPASS37=0;
+ *BYPASS40=0;
+ *BYPASS41=0x566600c3;
+ *DMACONFIG=0x0032616a;
+ *VSYNC=0;
+ *DMASTART=0;
+ while((*INTSTATUS&4)==0);
+ *INTCLEAR=*INTSTATUS&4;
+ while(*INTSTATUS&4);
+ FB+=240*2;
+ }
+ */
+ // data->fbi.fb = (uint16 *)data->physFB;
+ // data->fbi.fonts = (unsigned char *)data->physFonts;
FB_PRINTF(&data->fbi, "In preloader\\n");
-
uint32 psr = do_cpuGetPSR();
FB_PRINTF(&data->fbi, "PSR=%%x\\n", psr);
- if ((psr & 0xc0) != 0xc0)
+ if ((psr & 0xc0) != 0xc0) {
FB_PRINTF(&data->fbi, "ERROR: IRQS not off\\n");
+ FLASH(10);
+ }
if (fbOverlaps(data)) {
FB_PRINTF(&data->fbi, "Disabling framebuffer feedback\\n");
data->fbi.fb = 0;
}
-
+//FLASH(4)
// Copy tags to beginning of ram.
char *destTags = (char *)data->startRam + PHYSOFFSET_TAGS;
do_copy(destTags, data->tags, TAGSIZE);
+//FLASH(5)
FB_PRINTF(&data->fbi, "Tags relocated\\n");
@@ -277,6 +361,7 @@
char *destInitrd = (char *)data->startRam + PHYSOFFSET_INITRD;
int initrdCount = PAGE_ALIGN(data->initrdSize) / PAGE_SIZE;
do_copyPages(destInitrd, data->indexPages, kernelCount, initrdCount);
+//FLASH(6)
FB_PRINTF(&data->fbi, "Initrd relocated\\n");
@@ -310,10 +395,13 @@
}
FB_PRINTF(&data->fbi, "Jumping to Kernel...\\n");
-
+// flash(5,0);
// Boot
typedef void (*lin_t)(uint32 zero, uint32 mach, char *tags);
lin_t startfunc = (lin_t)destKernel;
+
+ FLASH(2);
+
startfunc(0, data->machtype, destTags);
}
@@ -551,11 +639,27 @@
return physAddrTram;
}
+/*
+volatile unsigned *const BYPASS33=(unsigned *)0xb2110184;
+volatile unsigned *const BYPASS34=(unsigned *)0xb2110188;
+volatile unsigned *const BYPASS35=(unsigned *)0xb211018c;
+volatile unsigned *const BYPASS37=(unsigned *)0xb2110194;
+volatile unsigned *const BYPASS40=(unsigned *)0xb21101a0;
+volatile unsigned *const BYPASS41=(unsigned *)0xb21101a4;
+volatile unsigned *const DMACONFIG=(unsigned *)0xb2110180;
+volatile unsigned *const VSYNC=(unsigned *)0xb210008c;
+volatile unsigned *const DMASTART=(unsigned *)0xb2110044;
+
+volatile unsigned *const INTSTATUS=(unsigned *)0xb2100024;
+volatile unsigned *const INTCLEAR=(unsigned *)0xb2100028;
+*/
// Launch a kernel loaded in memory.
static void
launchKernel(struct bootmem *bm)
{
+//fb_clear(&bm->pd->fbi);
+//exit(1);
// Prep the trampoline.
uint32 physAddrTram = setupTrampoline();
if (! physAddrTram)
@@ -566,6 +670,7 @@
Output("MMU setup: mmu=%p/%08x", virtAddrMmu, cpuGetMMU());
// Call per-arch setup.
+
int ret = Mach->preHardwareShutdown();
if (ret) {
Output(C_ERROR "Setup for machine shutdown failed");
@@ -578,13 +683,44 @@
take_control();
fb_clear(&bm->pd->fbi);
+ fb_printf(&bm->pd->fbi, "screen Cleared\n");
+//Sleep(100);
+fb_printf(&bm->pd->fbi, "Take control\n");
+//take_control();
+//fb_clear(&bm->pd->fbi);
+ /*
+ for(int i=0;i<10;i++) {
+
+ flash(1,0);
+ fb_printf(&bm->pd->fbi, "Flashing\n");
+ *BYPASS33=0x014000f0;
+ *BYPASS34=0x00700000;
+ *BYPASS35=0x000001e0;
+ *BYPASS37=0;
+ *BYPASS40=0;
+ *BYPASS41=0x566600c3;
+ *DMACONFIG=0x0032616a;
+ *VSYNC=0;
+ *DMASTART=0;
+ while(*INTSTATUS==0);
+ *INTCLEAR=*INTSTATUS;
+ fb_printf(&bm->pd->fbi, "status=%x\n",*INTSTATUS);
+ }
+
+ return_control();
+ Sleep(10000);
+ return;
+*/
+fb_printf(&bm->pd->fbi, "Took control\n");
+//Sleep(100);
fb_printf(&bm->pd->fbi, "HaRET boot\nShutting down hardware\n");
-
+//Sleep(100);
// Call per-arch boot prep function.
Mach->hardwareShutdown(&bm->pd->fbi);
fb_printf(&bm->pd->fbi, "Turning off MMU...\n");
-
+//Sleep(100);
+ //flash(1,0);
// Disable MMU and launch linux.
mmu_trampoline(physAddrTram, virtAddrMmu, bm->physExec, Mach->flushCache);
diff -ur -x CVS src/mach/arch-msm.cpp haret-msm/src/mach/arch-msm.cpp
--- src/mach/arch-msm.cpp 2007-10-30 10:32:20.000000000 +0100
+++ haret-msm/src/mach/arch-msm.cpp 2008-03-09 21:16:59.000000000 +0100
@@ -1,12 +1,18 @@
// Support for Qualcomm MSMxxxx cpus.
#include "script.h" // runMemScript
#include "arch-msm.h"
+extern "C" {
+ void cpuFlushCache_arm920();
+ void cpuFlushCache_arm926();
+ void cpuFlushCache_arm6();
+}
MachineMSM7500::MachineMSM7500()
{
name = "Generic MSM7500";
archname = "MSM7500";
CPUInfo[0] = L"MSM7500";
+ flushCache = cpuFlushCache_arm6;
}
diff -ur -x CVS src/wince/asmstuff.S haret-msm/src/wince/asmstuff.S
--- src/wince/asmstuff.S 2007-09-28 11:23:52.000000000 +0200
+++ haret-msm/src/wince/asmstuff.S 2008-03-18 22:00:27.000000000 +0100
@@ -37,12 +37,16 @@
mov pc, lr
+ movs pc,r14
+ subs pc,r14,#4
+ subs pc,r14,#8
@ Flush CPU caches on xscale - this MUST be called between
@ take_control()/return_control()
@
@ Dirties r0, r1
.global cpuFlushCache_xscale
cpuFlushCache_xscale:
+/*
@ Flush data cache
ldr r1, =junkdata
mov r0, #1024
@@ -56,7 +60,7 @@
mcr p15, 0, r0, c8, c7, 0 @ Invalidate I+D TLB
mcr p15, 0, r0, c7, c7, 0 @ Invalidate I+D caches & BTB
CPWAIT r0
-
+*/
mov pc, lr
@ Flush CPU caches on arm920 - this MUST be called between
@@ -65,6 +69,7 @@
@ Dirties r0, r1, r2
.global cpuFlushCache_arm920
cpuFlushCache_arm920:
+/*
mov r0, #0
mov r1, #(8-1) << 5 @ 8 segments
1: orr r2, r1,#(64-1)<<26 @ 64 entries
@@ -77,6 +82,7 @@
mcr p15, 0, r0, c7, c5, 0 @ invalidate I cache
mcr p15, 0, r0, c7, c10, 4 @ drain WB
mcr p15, 0, r0, c8, c7, 0 @ drain I+D TLBs
+*/
mov pc, r14
@ Flush CPU caches on arm925 - this MUST be called between
@@ -85,6 +91,7 @@
@ Dirties r0
.global cpuFlushCache_arm925
cpuFlushCache_arm925:
+/*
mov r0, #(256 - 1) << 4 @ 256 entries in segment
1: mrc p15, 0, r0, c7, c14, 2 @ test,clean,invalidate
subs r0, r0, #1 << 4
@@ -94,6 +101,7 @@
mcr p15, 0, r0, c7, c5, 0 @ invalidate I cache
mcr p15, 0, r0, c7, c10, 4 @ drain WB
mcr p15, 0, r0, c8, c7, 0 @ drain I+D TLBs
+*/
mov pc, r14
@ Flush CPU caches on arm926 - this MUST be called between
@@ -102,6 +110,7 @@
@ Dirties r0
.global cpuFlushCache_arm926
cpuFlushCache_arm926:
+/*
1: mrc p15, 0, r15, c7, c14, 3 @ test,clean,invalidate
bne 1b
@@ -109,6 +118,7 @@
mcr p15, 0, r0, c7, c5, 0 @ invalidate I cache
mcr p15, 0, r0, c7, c10, 4 @ drain WB
mcr p15, 0, r0, c8, c7, 0 @ drain I+D TLBs
+*/
mov pc, r14
@ Flush CPU caches on arm v6
@@ -144,10 +154,71 @@
@ r3 = cpu flush cache function
.section .text.trampoline
.global mmu_trampoline, mmu_trampoline_end
+/*
+wait:
+ str lr, [sp, #-4]!
+ subs lr, r0, #0
+ movle r0, #0
+ ldrle pc, [sp], #4
+ b x178
+ x13c: add r3, r0, r2
+ add r3, r3, r1
+ add r0, r3, ip
+ add r2, r2, #1
+ cmp r2, #32768
+ bne x13c
+ add r1, r1, #1
+ cmp r1, #256
+ bne x170
+ add ip, ip, #1
+ cmp lr, ip
+ ldreq pc, [sp], #4
+ b x180
+ x170: mov r2, #0
+ b x13c
+ x178: mov r0, #0
+ mov ip, r0
+ x180: mov r1, #0
+ b x170
+flash:
+ stmdb sp!, {r4, r5, r6, r7, lr}
+ mov r7, r0
+ cmp r1, #0
+ movne r3, #-1459617792
+ addne r3, r3, #3145728
+ addne r5, r3, #3072
+ moveq r3, #-1845493760
+ addeq r3, r3, #10485760
+ addeq r5, r3, #3072
+ mov r3, #2048
+ str r3, [r5]
+ mov r0, #5
+ bl wait
+ cmp r7, #0
+ ble x1fc
+ mov r4, #0
+ mov r6, #6144
+x1cc: mov r0, #1
+ bl wait
+ str r6, [r5]
+ mov r0, #1
+ bl wait
+ mov r3, #2048
+ str r3, [r5]
+ mov r0, #1
+ bl wait
+ add r4, r4, #1
+ cmp r7, r4
+ bne x1cc
+x1fc: mov r0, #5
+ bl wait
+ ldmia sp!, {r4, r5, r6, r7, pc}
+*/
mmu_trampoline:
@ Store previous registers on stack.
stmdb sp, {r4-r14}
+
@ Write back all cpu caches
mov r4, r0
mov r5, r1
@@ -155,6 +226,68 @@
mov lr, pc
mov pc, r3
+/*
+ mov r0,#3
+ mov r1,#0
+ bl flash
+*/
+ /*
+ * map some RAM to same addresses.
+ */
+
+// mcr p15, 0, r4, c2, c0, 0 @ get page table address
+ mov r1,#0x00000000 // r1 is phys and virt address
+1: mov r2,r1,lsr#20 @ r2=adr >> 20
+ mov r0,r2,asl#20 @ r0=adr & 0xfff00000
+ orr r0,r0,#0x00000C00
+ orr r0, r0, #0x00000002 @ r0=r0 | 0xc02
+// mov r3,r1,lsr#20
+// cmp r3,#0x007
+// orreq r0,#0x8 // buffer ?
+// biceq r0,#0x800
+
+ mov r3,r1,lsr#24
+ cmp r3,#0xa9
+ orreq r0,#0x2000 // tex
+// orreq r0,#0x4
+ cmp r3,#0xaa
+ orreq r0,#0x2000 // tex
+// orreq r0,#0x4 // + buffer
+ cmp r3,#0xe0
+ orreq r0,#0x2000 // tex
+// orreq r0,#0x4
+ subeq r0,#0x40000000
+
+ mov r3,r1,lsr#28
+ cmp r3,#0x1
+ orreq r0,#0xc // cache + buffer
+ // mov r3,r1,lsr#28
+ // cmp r3,#0xc
+ // subeq r0,#0xb0000000
+ // orreq r0,#0xc
+ mov r3,r1,lsr#20
+ cmp r3,#0xae0
+ strne r0,[r5,r2,lsl #2]
+ adds r1,r1,#1<<20
+ // cmp r1,#0
+ // cmp r1,#0xfff00000
+ bne 1b
+ mov r1,#0x88000000
+ add r1,#0x15
+ mcr p15, 0, r1, c15, c2, 4
+// move page tables
+// to 0x10004000
+ mov r1,#0x10000000
+ add r1,#0x00004000
+ mov r0,#0
+1: ldr r3,[r5,r0,lsl #2]
+ str r3,[r1,r0,lsl #2]
+ add r0,r0,#1
+ cmp r0,#0x1000
+ bne 1b
+
+ mrc p15, 0, r1, c2, c0, 0
+
@ Turn off mapping for this code
mov r1, r4, lsr #20
mov r0, r1, asl #20 @ r0 = funcaddr & 0xfff00000
@@ -162,29 +295,64 @@
orr r0, r0, #0x00000002 @ r0 |= 0xC02
str r0, [r5, r1, asl #2] @ mmu[funcaddr>>20] = r0
+ mrc p15, 0, r1, c2, c0, 0
+/*
+ mov r0,#4
+ mov r1,#0
+ bl flash
+*/
+/*
@ Force MMU update and invalidate I cache
mov r0, #0
mcr p15, 0, r0, c7, c10, 4 @ Drain write buffer
mcr p15, 0, r0, c8, c7, 0 @ Invalidate I+D TLB
mcr p15, 0, r0, c7, c5, 0 @ Invalidate I cache & BTB
CPWAIT r0
-
+*/
+// bl lton
@ Jump to code with shared virtual/physical mapping
add pc, r4, #(1f - mmu_trampoline)
+lton: mov r1, #-1845493760
+ add r1, r1, #10485760
+ add r1, r1, #3072
+ mov r0, #6144
+ str r0,[r1]
+ mov pc, r14
+
+ltoff: mov r1, #-1845493760
+ add r1, r1, #10485760
+ add r1, r1, #3072
+ mov r0, #2048
+ str r0,[r1]
+ mov pc, r14
+
+
1: @ Code is running at a vm address that is the same as its
- @ physical address. Now disable the MMU.
+ @ physical address. Now disable the MMU (or not).
+
+/* mov r0,#5
+ mov r1,#0
+ bl flash
+*/
+// bl lton
+// b 1b
+
+/*
mrc p15, 0, r0, c1, c0, 0
bic r0, r0, #5 @ MMU & Dcache off
bic r0, r0, #0x1000 @ Icache off
mcr p15, 0, r0, c1, c0, 0 @ disable the MMU & caches
CPWAIT r0
+*/
+/*
mov r0, #0
mcr p15, 0, r0, c13, c0, 0 @ clear PID
mcr p15, 0, r0, c8, c7, 0 @ invalidate I+D TLB
mcr p15, 0, r0, c7, c5, 0 @ Invalidate I cache & BTB
CPWAIT r0
+*/
@ MMU is now disabled. Call function.
mov pc, r6