rendered paste bodyTiming constraint: TS_dcm_0_dcm_0_CLK0_BUF = PERIOD TIMEGRP
"dcm_0_dcm_0_CLK0_BUF" TS_sys_clk_pin HIGH 50%;
141952627 items analyzed, 29 timing errors detected. (29 setup errors, 0 hold errors)
Minimum period is 10.859ns.
--------------------------------------------------------------------------------
Slack: -0.859ns (requirement - (data path - clock path skew + uncertainty))
Source: sha_sysace_0/sha_sysace_0/USER_LOGIC_I/sha512/sha512_comp/a_t_38_BRB0 (FF)
Destination: sha_sysace_0/sha_sysace_0/USER_LOGIC_I/sha512/sha512_comp/a_t_63_BRB1 (FF)
Requirement: 10.000ns
Data Path Delay: 10.745ns (Levels of Logic = 25)
Clock Path Skew: -0.054ns
Source Clock: sys_clk_s rising at 0.000ns
Destination Clock: sys_clk_s rising at 10.000ns
Clock Uncertainty: 0.060ns
Clock Uncertainty: 0.060ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE
Total System Jitter (TSJ): 0.000ns
Total Input Jitter (TIJ): 0.000ns
Discrete Jitter (DJ): 0.120ns
Phase Error (PE): 0.000ns
Maximum Data Path: sha_sysace_0/sha_sysace_0/USER_LOGIC_I/sha512/sha512_comp/a_t_38_BRB0 to sha_sysace_0/sha_sysace_0/USER_LOGIC_I/sha512/sha512_comp/a_t_63_BRB1
Location Delay type Delay(ns) Physical Resource
Logical Resource(s)
------------------------------------------------- -------------------
SLICE_X15Y65.YQ Tcko 0.291 sha_sysace_0/sha_sysace_0/USER_LOGIC_I/sha512/sha512_comp/a_t_38_BRB0
sha_sysace_0/sha_sysace_0/USER_LOGIC_I/sha512/sha512_comp/a_t_38_BRB0
SLICE_X17Y69.G2 net (fanout=54) 0.696 sha_sysace_0/sha_sysace_0/USER_LOGIC_I/sha512/sha512_comp/a_t_38_BRB0
SLICE_X17Y69.Y Tilo 0.165 sha_sysace_0/sha_sysace_0/USER_LOGIC_I/sha512/sha512_comp/e_t_62_BRB2
sha_sysace_0/sha_sysace_0/USER_LOGIC_I/sha512/sha512_comp/e_t_mux0001<62>1
SLICE_X30Y52.G4 net (fanout=6) 0.979 sha_sysace_0/sha_sysace_0/USER_LOGIC_I/sha512/sha512_comp/e_t<62>
SLICE_X30Y52.Y Tilo 0.166 sha_sysace_0/sha_sysace_0/USER_LOGIC_I/sha512/sha512_comp/Mxor_s1_27_xo<1>1_FRB_BRB3
sha_sysace_0/sha_sysace_0/USER_LOGIC_I/sha512/sha512_comp/Madd_t1_addsub0001C20
SLICE_X18Y53.BX net (fanout=1) 0.549 sha_sysace_0/sha_sysace_0/USER_LOGIC_I/sha512/sha512_comp/Madd_t1_addsub0001C20
SLICE_X18Y53.COUT Tbxcy 0.658 sha_sysace_0/sha_sysace_0/USER_LOGIC_I/sha512/sha512_comp/Madd_t1_addsub0001_Madd_cy<23>
sha_sysace_0/sha_sysace_0/USER_LOGIC_I/sha512/sha512_comp/Madd_t1_addsub0001_Madd_cy<22>
sha_sysace_0/sha_sysace_0/USER_LOGIC_I/sha512/sha512_comp/Madd_t1_addsub0001_Madd_cy<23>
SLICE_X18Y54.CIN net (fanout=1) 0.000 sha_sysace_0/sha_sysace_0/USER_LOGIC_I/sha512/sha512_comp/Madd_t1_addsub0001_Madd_cy<23>
SLICE_X18Y54.COUT Tbyp 0.076 sha_sysace_0/sha_sysace_0/USER_LOGIC_I/sha512/sha512_comp/e_t<38>
sha_sysace_0/sha_sysace_0/USER_LOGIC_I/sha512/sha512_comp/Madd_t1_addsub0001_Madd_cy<24>
sha_sysace_0/sha_sysace_0/USER_LOGIC_I/sha512/sha512_comp/Madd_t1_addsub0001_Madd_cy<25>
SLICE_X18Y55.CIN net (fanout=1) 0.000 sha_sysace_0/sha_sysace_0/USER_LOGIC_I/sha512/sha512_comp/Madd_t1_addsub0001_Madd_cy<25>
SLICE_X18Y55.YMUX Tciny 0.438 sha_sysace_0/sha_sysace_0/USER_LOGIC_I/sha512/sha512_comp/e_t_47_BRB1
sha_sysace_0/sha_sysace_0/USER_LOGIC_I/sha512/sha512_comp/Madd_t1_addsub0001_Madd_cy<26>
sha_sysace_0/sha_sysace_0/USER_LOGIC_I/sha512/sha512_comp/Madd_t1_addsub0001_Madd_xor<27>
SLICE_X20Y55.F4 net (fanout=3) 0.535 sha_sysace_0/sha_sysace_0/USER_LOGIC_I/sha512/sha512_comp/t1_addsub0001<27>
SLICE_X20Y55.X Tilo 0.166 sha_sysace_0/sha_sysace_0/USER_LOGIC_I/sha512_hash_out<134>
sha_sysace_0/sha_sysace_0/USER_LOGIC_I/sha512/sha512_comp/Madd_t1C261
SLICE_X16Y56.BX net (fanout=1) 0.481 sha_sysace_0/sha_sysace_0/USER_LOGIC_I/sha512/sha512_comp/Madd_t1C26
SLICE_X16Y56.COUT Tbxcy 0.658 sha_sysace_0/sha_sysace_0/USER_LOGIC_I/sha512/sha512_comp/Madd_t1_Madd_cy<29>
sha_sysace_0/sha_sysace_0/USER_LOGIC_I/sha512/sha512_comp/Madd_t1_Madd_cy<28>
sha_sysace_0/sha_sysace_0/USER_LOGIC_I/sha512/sha512_comp/Madd_t1_Madd_cy<29>
SLICE_X16Y57.CIN net (fanout=1) 0.000 sha_sysace_0/sha_sysace_0/USER_LOGIC_I/sha512/sha512_comp/Madd_t1_Madd_cy<29>
SLICE_X16Y57.COUT Tbyp 0.076 sha_sysace_0/sha_sysace_0/USER_LOGIC_I/sha512/sha512_comp/Madd_t1_Madd_cy<31>
sha_sysace_0/sha_sysace_0/USER_LOGIC_I/sha512/sha512_comp/Madd_t1_Madd_cy<30>
sha_sysace_0/sha_sysace_0/USER_LOGIC_I/sha512/sha512_comp/Madd_t1_Madd_cy<31>
SLICE_X16Y58.CIN net (fanout=1) 0.000 sha_sysace_0/sha_sysace_0/USER_LOGIC_I/sha512/sha512_comp/Madd_t1_Madd_cy<31>
SLICE_X16Y58.YMUX Tciny 0.438 sha_sysace_0/sha_sysace_0/USER_LOGIC_I/sha512/sha512_comp/Madd_t1_Madd_cy<33>
sha_sysace_0/sha_sysace_0/USER_LOGIC_I/sha512/sha512_comp/Madd_t1_Madd_cy<32>
sha_sysace_0/sha_sysace_0/USER_LOGIC_I/sha512/sha512_comp/Madd_t1_Madd_xor<33>
SLICE_X8Y59.G3 net (fanout=4) 0.975 sha_sysace_0/sha_sysace_0/USER_LOGIC_I/sha512/sha512_comp/t1<33>
SLICE_X8Y59.Y Tilo 0.166 sha_sysace_0/sha_sysace_0/USER_LOGIC_I/sha512/sha512_comp/f_t<15>
sha_sysace_0/sha_sysace_0/USER_LOGIC_I/sha512/sha512_comp/Madd_a_t_addsub0000C321
SLICE_X19Y61.BX net (fanout=1) 0.658 sha_sysace_0/sha_sysace_0/USER_LOGIC_I/sha512/sha512_comp/Madd_a_t_addsub0000C32
SLICE_X19Y61.COUT Tbxcy 0.646 sha_sysace_0/sha_sysace_0/USER_LOGIC_I/sha512/sha512_comp/a_t_34_BRB1
sha_sysace_0/sha_sysace_0/USER_LOGIC_I/sha512/sha512_comp/Madd_a_t_addsub0000_Madd_cy<34>
sha_sysace_0/sha_sysace_0/USER_LOGIC_I/sha512/sha512_comp/Madd_a_t_addsub0000_Madd_cy<35>
SLICE_X19Y62.CIN net (fanout=1) 0.000 sha_sysace_0/sha_sysace_0/USER_LOGIC_I/sha512/sha512_comp/Madd_a_t_addsub0000_Madd_cy<35>
SLICE_X19Y62.COUT Tbyp 0.074 sha_sysace_0/sha_sysace_0/USER_LOGIC_I/sha512/sha512_comp/a_t_36_BRB1
sha_sysace_0/sha_sysace_0/USER_LOGIC_I/sha512/sha512_comp/Madd_a_t_addsub0000_Madd_cy<36>
sha_sysace_0/sha_sysace_0/USER_LOGIC_I/sha512/sha512_comp/Madd_a_t_addsub0000_Madd_cy<37>
SLICE_X19Y63.CIN net (fanout=1) 0.000 sha_sysace_0/sha_sysace_0/USER_LOGIC_I/sha512/sha512_comp/Madd_a_t_addsub0000_Madd_cy<37>
SLICE_X19Y63.COUT Tbyp 0.074 sha_sysace_0/sha_sysace_0/USER_LOGIC_I/sha512/sha512_comp/a_t_38_BRB1
sha_sysace_0/sha_sysace_0/USER_LOGIC_I/sha512/sha512_comp/Madd_a_t_addsub0000_Madd_cy<38>
sha_sysace_0/sha_sysace_0/USER_LOGIC_I/sha512/sha512_comp/Madd_a_t_addsub0000_Madd_cy<39>
SLICE_X19Y64.CIN net (fanout=1) 0.000 sha_sysace_0/sha_sysace_0/USER_LOGIC_I/sha512/sha512_comp/Madd_a_t_addsub0000_Madd_cy<39>
SLICE_X19Y64.COUT Tbyp 0.074 sha_sysace_0/sha_sysace_0/USER_LOGIC_I/sha512/sha512_comp/a_t_40_BRB1
sha_sysace_0/sha_sysace_0/USER_LOGIC_I/sha512/sha512_comp/Madd_a_t_addsub0000_Madd_cy<40>
sha_sysace_0/sha_sysace_0/USER_LOGIC_I/sha512/sha512_comp/Madd_a_t_addsub0000_Madd_cy<41>
SLICE_X19Y65.CIN net (fanout=1) 0.000 sha_sysace_0/sha_sysace_0/USER_LOGIC_I/sha512/sha512_comp/Madd_a_t_addsub0000_Madd_cy<41>
SLICE_X19Y65.COUT Tbyp 0.074 sha_sysace_0/sha_sysace_0/USER_LOGIC_I/sha512/sha512_comp/a_t_42_BRB1
sha_sysace_0/sha_sysace_0/USER_LOGIC_I/sha512/sha512_comp/Madd_a_t_addsub0000_Madd_cy<42>
sha_sysace_0/sha_sysace_0/USER_LOGIC_I/sha512/sha512_comp/Madd_a_t_addsub0000_Madd_cy<43>
SLICE_X19Y66.CIN net (fanout=1) 0.000 sha_sysace_0/sha_sysace_0/USER_LOGIC_I/sha512/sha512_comp/Madd_a_t_addsub0000_Madd_cy<43>
SLICE_X19Y66.COUT Tbyp 0.074 sha_sysace_0/sha_sysace_0/USER_LOGIC_I/sha512/sha512_comp/a_t_44_BRB1
sha_sysace_0/sha_sysace_0/USER_LOGIC_I/sha512/sha512_comp/Madd_a_t_addsub0000_Madd_cy<44>
sha_sysace_0/sha_sysace_0/USER_LOGIC_I/sha512/sha512_comp/Madd_a_t_addsub0000_Madd_cy<45>
SLICE_X19Y67.CIN net (fanout=1) 0.000 sha_sysace_0/sha_sysace_0/USER_LOGIC_I/sha512/sha512_comp/Madd_a_t_addsub0000_Madd_cy<45>
SLICE_X19Y67.COUT Tbyp 0.074 sha_sysace_0/sha_sysace_0/USER_LOGIC_I/sha512/sha512_comp/a_t_46_BRB1
sha_sysace_0/sha_sysace_0/USER_LOGIC_I/sha512/sha512_comp/Madd_a_t_addsub0000_Madd_cy<46>
sha_sysace_0/sha_sysace_0/USER_LOGIC_I/sha512/sha512_comp/Madd_a_t_addsub0000_Madd_cy<47>
SLICE_X19Y68.CIN net (fanout=1) 0.000 sha_sysace_0/sha_sysace_0/USER_LOGIC_I/sha512/sha512_comp/Madd_a_t_addsub0000_Madd_cy<47>
SLICE_X19Y68.COUT Tbyp 0.074 sha_sysace_0/sha_sysace_0/USER_LOGIC_I/sha512/sha512_comp/a_t_48_BRB1
sha_sysace_0/sha_sysace_0/USER_LOGIC_I/sha512/sha512_comp/Madd_a_t_addsub0000_Madd_cy<48>
sha_sysace_0/sha_sysace_0/USER_LOGIC_I/sha512/sha512_comp/Madd_a_t_addsub0000_Madd_cy<49>
SLICE_X19Y69.CIN net (fanout=1) 0.000 sha_sysace_0/sha_sysace_0/USER_LOGIC_I/sha512/sha512_comp/Madd_a_t_addsub0000_Madd_cy<49>
SLICE_X19Y69.COUT Tbyp 0.074 sha_sysace_0/sha_sysace_0/USER_LOGIC_I/sha512/sha512_comp/a_t_50_BRB1
sha_sysace_0/sha_sysace_0/USER_LOGIC_I/sha512/sha512_comp/Madd_a_t_addsub0000_Madd_cy<50>
sha_sysace_0/sha_sysace_0/USER_LOGIC_I/sha512/sha512_comp/Madd_a_t_addsub0000_Madd_cy<51>
SLICE_X19Y70.CIN net (fanout=1) 0.000 sha_sysace_0/sha_sysace_0/USER_LOGIC_I/sha512/sha512_comp/Madd_a_t_addsub0000_Madd_cy<51>
SLICE_X19Y70.COUT Tbyp 0.074 sha_sysace_0/sha_sysace_0/USER_LOGIC_I/sha512/sha512_comp/a_t_52_BRB1
sha_sysace_0/sha_sysace_0/USER_LOGIC_I/sha512/sha512_comp/Madd_a_t_addsub0000_Madd_cy<52>
sha_sysace_0/sha_sysace_0/USER_LOGIC_I/sha512/sha512_comp/Madd_a_t_addsub0000_Madd_cy<53>
SLICE_X19Y71.CIN net (fanout=1) 0.000 sha_sysace_0/sha_sysace_0/USER_LOGIC_I/sha512/sha512_comp/Madd_a_t_addsub0000_Madd_cy<53>
SLICE_X19Y71.COUT Tbyp 0.074 sha_sysace_0/sha_sysace_0/USER_LOGIC_I/sha512/sha512_comp/a_t_54_BRB1
sha_sysace_0/sha_sysace_0/USER_LOGIC_I/sha512/sha512_comp/Madd_a_t_addsub0000_Madd_cy<54>
sha_sysace_0/sha_sysace_0/USER_LOGIC_I/sha512/sha512_comp/Madd_a_t_addsub0000_Madd_cy<55>
SLICE_X19Y72.CIN net (fanout=1) 0.000 sha_sysace_0/sha_sysace_0/USER_LOGIC_I/sha512/sha512_comp/Madd_a_t_addsub0000_Madd_cy<55>
SLICE_X19Y72.COUT Tbyp 0.074 sha_sysace_0/sha_sysace_0/USER_LOGIC_I/sha512/sha512_comp/a_t_56_BRB1
sha_sysace_0/sha_sysace_0/USER_LOGIC_I/sha512/sha512_comp/Madd_a_t_addsub0000_Madd_cy<56>
sha_sysace_0/sha_sysace_0/USER_LOGIC_I/sha512/sha512_comp/Madd_a_t_addsub0000_Madd_cy<57>
SLICE_X19Y73.CIN net (fanout=1) 0.000 sha_sysace_0/sha_sysace_0/USER_LOGIC_I/sha512/sha512_comp/Madd_a_t_addsub0000_Madd_cy<57>
SLICE_X19Y73.COUT Tbyp 0.074 sha_sysace_0/sha_sysace_0/USER_LOGIC_I/sha512/sha512_comp/a_t_58_BRB1
sha_sysace_0/sha_sysace_0/USER_LOGIC_I/sha512/sha512_comp/Madd_a_t_addsub0000_Madd_cy<58>
sha_sysace_0/sha_sysace_0/USER_LOGIC_I/sha512/sha512_comp/Madd_a_t_addsub0000_Madd_cy<59>
SLICE_X19Y74.CIN net (fanout=1) 0.000 sha_sysace_0/sha_sysace_0/USER_LOGIC_I/sha512/sha512_comp/Madd_a_t_addsub0000_Madd_cy<59>
SLICE_X19Y74.COUT Tbyp 0.074 sha_sysace_0/sha_sysace_0/USER_LOGIC_I/sha512/sha512_comp/a_t_60_BRB1
sha_sysace_0/sha_sysace_0/USER_LOGIC_I/sha512/sha512_comp/Madd_a_t_addsub0000_Madd_cy<60>
sha_sysace_0/sha_sysace_0/USER_LOGIC_I/sha512/sha512_comp/Madd_a_t_addsub0000_Madd_cy<61>
SLICE_X19Y75.CIN net (fanout=1) 0.000 sha_sysace_0/sha_sysace_0/USER_LOGIC_I/sha512/sha512_comp/Madd_a_t_addsub0000_Madd_cy<61>
SLICE_X19Y75.YMUX Tciny 0.427 sha_sysace_0/sha_sysace_0/USER_LOGIC_I/sha512/sha512_comp/a_t_62_BRB1
sha_sysace_0/sha_sysace_0/USER_LOGIC_I/sha512/sha512_comp/Madd_a_t_addsub0000_Madd_cy<62>
sha_sysace_0/sha_sysace_0/USER_LOGIC_I/sha512/sha512_comp/Madd_a_t_addsub0000_Madd_xor<63>
SLICE_X17Y74.BY net (fanout=1) 0.290 sha_sysace_0/sha_sysace_0/USER_LOGIC_I/sha512/sha512_comp/a_t_addsub0000<63>
SLICE_X17Y74.CLK Tdick 0.249 sha_sysace_0/sha_sysace_0/USER_LOGIC_I/sha512/sha512_comp/a_t_63_BRB1
sha_sysace_0/sha_sysace_0/USER_LOGIC_I/sha512/sha512_comp/a_t_63_BRB1
------------------------------------------------- ---------------------------
Total 10.745ns (5.582ns logic, 5.163ns route)
(51.9% logic, 48.1% route)