rendered paste body/*
* include/configs/corgi.h
*
* Configuration settings for the Sharp Zaurus SL-C7x0/C860.
*
* (C) Copyright 2006 Alexander Chukov <sash@pdaXrom.org>
*
* portions from adsvix board configuration:
* (C) Copyright 2004
* Robert Whaley, Applied Data Systems, Inc. rwhaley@applieddata.net
* (C) Copyright 2002
* Kyle Harris, Nexus Technologies, Inc. kharris@nexus-tech.net
* (C) Copyright 2002
* Sysgo Real-Time Solutions, GmbH <www.elinos.com>
* Marius Groeger <mgroeger@sysgo.de>
*
* See file CREDITS for list of people who contributed to this
* project.
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of
* the License, or (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
* MA 02111-1307 USA
*/
#ifndef __CONFIG_H
#define __CONFIG_H
#define CONFIG_SKIP_LOWLEVEL_INIT
#undef SKIP_CONFIG_RELOCATE_UBOOT
#undef CONFIG_HARD_I2C
/*
* High Level Configuration Options
* (easy to change)
*/
#define CONFIG_PXA250 1 /* This is an PXA255 CPU */
#define CONFIG_CORGI 1 /* on Sharp Zaurus Corgi */
#define CONFIG_MMC 1
#define BOARD_LATE_INIT 1
#undef CONFIG_USE_IRQ /* we don't need IRQ/FIQ stuff */
#define RTC 1
/*
* Size of malloc() pool
*/
//#define CFG_MALLOC_LEN (CFG_ENV_SIZE + 128*1024)
#define CFG_MALLOC_LEN (CFG_ENV_SIZE + 256*1024)
#define CFG_GBL_DATA_SIZE 128 /* size in bytes reserved for initial data */
/*
* select serial console configuration
*/
#define CONFIG_FFUART 1 /* we use FFUART on Mainstone */
/* allow to overwrite serial and ethaddr */
#define CONFIG_BAUDRATE 115200
#define CONFIG_DOS_PARTITION 1
#undef CONFIG_SHOW_BOOT_PROGRESS
#if 1
#define CONFIG_BOOTDELAY 1
#define CONFIG_AUTOBOOT_PROMPT "Autobooting in %d seconds\n"
#define CONFIG_BOOTCOMMAND \
"if testkey 101 ; " \
"then " \
"nand read.logical 0xa0800000 0x00060000 0x00540000; " \
"setenv bootargs console=ttyS0,115200 console=tty1 root=/dev/ram rw ramdisk_size=8192; " \
"bootm; " \
"fi; " \
"if testkey 2 ; " \
"then " \
"nand read.logical 0xa0800000 0x005a0000 0x00160000; " \
"setenv bootargs console=ttyS0,115200 console=tty1 root=/dev/mmcblk0p1; " \
"bootm; " \
"fi; " \
"if testkey 18 ; " \
"then " \
"nand read.logical 0xa0800000 0x005a0000 0x00160000; " \
"setenv bootargs console=ttyS0,115200 console=tty1 root=/dev/hda1; " \
"bootm; " \
"fi; " \
"if testkey 3 ; " \
"then " \
"nand read.logical 0xa0800000 0x005a0000 0x00160000; " \
"setenv bootargs console=ttyS0,115200 console=tty1 root=/dev/hdc1; " \
"bootm; " \
"fi; " \
"nand read.logical 0xa0800000 0x005a0000 0x00160000; " \
"setenv bootargs console=ttyS0,115200 console=tty1 root=/dev/mtdblock2 rootfstype=jffs2; " \
"bootm; "
#else
#define CONFIG_BOOTCOMMAND "" // "run boot_flash"
#endif
#define CONFIG_BOOTARGS "console=ttyS0,115200 console=tty1 root=/dev/ram rw ramdisk_size=8192"
#define CONFIG_SETUP_MEMORY_TAGS 1
#define CONFIG_CMDLINE_TAG 1 /* enable passing of ATAGs */
#define CONFIG_INITRD_TAG 1
#define CONFIG_COMMANDS (( \
CONFIG_CMD_DFL | \
CFG_CMD_NAND | \
CFG_CMD_JFFS2 \
) & ~( \
CFG_CMD_NET | \
CFG_CMD_FLASH | \
CFG_CMD_IMLS \
))
// CFG_CMD_ENV
/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */
//#include <cmd_confdefs.h>
#define CFG_CMD_LOADS 0x00000002ULL /* loads */
#define CFG_CMD_LOADB 0x00000004ULL /* loadb */
#define CFG_CMD_CACHE 0x00000010ULL /* icache, dcache */
#define CFG_CMD_FLASH 0x00000020ULL /* flinfo, erase, protect */
#define CFG_CMD_MEMORY 0x00000040ULL /* md, mm, nm, mw, cp, cmp, */
/* crc, base, loop, mtest */
#define CFG_CMD_ENV 0x00000100ULL /* saveenv */
#define CFG_CMD_PCMCIA 0x00000400ULL /* PCMCIA support */
#define CFG_CMD_IDE 0x00000800ULL /* IDE harddisk support */
#define CFG_CMD_IRQ 0x00002000ULL /* irqinfo */
#define CFG_CMD_CONSOLE 0x00008000ULL /* coninfo */
#define CFG_CMD_ASKENV 0x00020000ULL /* ask for env variable */
#define CFG_CMD_RUN 0x00040000ULL /* run command in env variable */
#define CFG_CMD_ECHO 0x00080000ULL /* echo arguments */
#define CFG_CMD_REGINFO 0x00200000ULL /* Register dump */
#define CFG_CMD_DATE 0x00800000ULL /* support for RTC, date/time...*/
#define CFG_CMD_AUTOSCRIPT 0x10000000ULL /* Autoscript Support */
#define CFG_CMD_BSP 0x80000000ULL /* Board Specific functions */
#define CFG_CMD_MISC 0x0000000200000000ULL /* Misc functions like sleep etc*/
#define CFG_CMD_JFFS2 0x0000001000000000ULL /* JFFS2 Support */
#define CFG_CMD_DIAG 0x0000008000000000ULL /* Diagnostics */
#define CFG_CMD_HWFLOW 0x0000020000000000ULL /* RTS/CTS hw flow control */
#define CFG_CMD_SAVES 0x0000040000000000ULL /* save S record dump */
#define CFG_CMD_NAND 0x0000800000000000ULL /* NAND support */
#define CFG_CMD_MMC 0x0008000000000000ULL /* MMC support */
#define CFG_CMD_FAT 0x0010000000000000ULL /* FAT support */
#define CFG_CMD_ITEST 0x0040000000000000ULL /* Integer (and string) test */
#define CFG_CMD_EXT2 0x1000000000000000ULL /* EXT2 Support */
#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
#define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */
#define CONFIG_KGDB_SER_INDEX 2 /* which serial port to use */
#endif
/*
* Miscellaneous configurable options
*/
#define CFG_HUSH_PARSER 1
#define CFG_PROMPT_HUSH_PS2 "> "
#define CFG_LONGHELP /* undef to save memory */
#define CFG_PROMPT "U-Boot> " /* Monitor Command Prompt */
#define CFG_CBSIZE 256 /* Console I/O Buffer Size */
#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */
#define CFG_MAXARGS 16 /* max number of command args */
#define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */
#define CFG_DEVICE_NULLDEV 1
#define CFG_MEMTEST_START 0xa0400000 /* memtest works on */
#define CFG_MEMTEST_END 0xa0800000 /* 4 ... 8 MB in DRAM */
#undef CFG_CLKS_IN_HZ /* everything, incl board info, in Hz */
#define CFG_LOAD_ADDR 0xa0800000 /* default load address */
#define CFG_HZ 3686400 /* incrementer freq: 3.6864 MHz */
#define CFG_CPUSPEED 0x207 /* need to look more closely, I think this is Turbo = 2x, L=91Mhz */
/* valid baudrates */
#define CFG_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200 }
#define CFG_MMC_BASE 0xF0000000
/*
* Stack sizes
*
* The stack sizes are set up in start.S using the settings below
*/
#define CONFIG_STACKSIZE (128*1024) /* regular stack */
#ifdef CONFIG_USE_IRQ
#define CONFIG_STACKSIZE_IRQ (4*1024) /* IRQ stack */
#define CONFIG_STACKSIZE_FIQ (4*1024) /* FIQ stack */
#endif
/*
* Physical Memory Map
*/
#define CONFIG_NR_DRAM_BANKS 4 /* we have 2 banks of DRAM */
#define PHYS_SDRAM_1 0xa0000000 /* SDRAM Bank #1 */
#define PHYS_SDRAM_1_SIZE 0x04000000 /* 64 MB */
#define PHYS_SDRAM_2 0xa4000000 /* SDRAM Bank #2 */
#define PHYS_SDRAM_2_SIZE 0x00000000 /* 0 MB */
#define PHYS_SDRAM_3 0xa8000000 /* SDRAM Bank #3 */
#define PHYS_SDRAM_3_SIZE 0x00000000 /* 0 MB */
#define PHYS_SDRAM_4 0xac000000 /* SDRAM Bank #4 */
#define PHYS_SDRAM_4_SIZE 0x00000000 /* 0 MB */
#define PHYS_FLASH_1 0xd4000000 /* Flash Bank #1 */
#define CFG_DRAM_BASE 0xa0000000
#define CFG_DRAM_SIZE 0x04000000
#define CFG_FLASH_BASE PHYS_FLASH_1
/*
* GPIO settings for Mainstone
*/
#define CFG_GPSR0_VAL 0x00708800
#define CFG_GPSR1_VAL 0x03cf0002
#define CFG_GPSR2_VAL 0x0021FC00
#define CFG_GPSR3_VAL 0x00000000
#define CFG_GPCR0_VAL 0x00001000
#define CFG_GPCR1_VAL 0x00000000
#define CFG_GPCR2_VAL 0x00000000
#define CFG_GPCR3_VAL 0x00000000
#define CFG_GPDR0_VAL 0xC27B9C04
#define CFG_GPDR1_VAL 0x00EFAA83
#define CFG_GPDR2_VAL 0x0E23FC00
#define CFG_GPDR3_VAL 0x001E1F81
#define CFG_GAFR0_L_VAL 0x94F00000
#define CFG_GAFR0_U_VAL 0x015A859A
#define CFG_GAFR1_L_VAL 0x999A955A
#define CFG_GAFR1_U_VAL 0x0005A4AA
#define CFG_GAFR2_L_VAL 0x6AA00000
#define CFG_GAFR2_U_VAL 0x55A8041A
#define CFG_GAFR3_L_VAL 0x56AA955A
#define CFG_GAFR3_U_VAL 0x00000001
#define CFG_PSSR_VAL 0x20 // ???????????
/*
* PCMCIA and CF Interfaces
*/
#define CFG_MECR_VAL 0x00000001
#define CFG_MCMEM0_VAL 0x00010204
#define CFG_MCMEM1_VAL 0x00010204
#define CFG_MCATT0_VAL 0x00010204
#define CFG_MCATT1_VAL 0x00010204
#define CFG_MCIO0_VAL 0x0000c108
#define CFG_MCIO1_VAL 0x0001c108
//#define CONFIG_PXA_PCMCIA 1
//#define CONFIG_PXA_IDE 1
#define CONFIG_PCMCIA_SLOT_A 1
/* just to keep build system happy */
#define CFG_PCMCIA_MEM_ADDR 0x28000000
#define CFG_PCMCIA_MEM_SIZE 0x04000000
#define CFG_IDE_MAXBUS 1
/* max. 1 IDE bus */
#define CFG_IDE_MAXDEVICE 1
/* max. 1 drive per IDE bus */
#define CFG_ATA_IDE0_OFFSET 0x0000
#define CFG_ATA_BASE_ADDR 0x20000000
/* Offset for data I/O */
#define CFG_ATA_DATA_OFFSET 0x1f0
/* Offset for normal register accesses */
#define CFG_ATA_REG_OFFSET 0x1f0
/* Offset for alternate registers */
#define CFG_ATA_ALT_OFFSET 0x3f0
#define CFG_NO_FLASH 1
#define CFG_MAX_FLASH_BANKS 1 /* max number of memory banks */
#define CFG_MAX_FLASH_SECT 512 /* max number of sectors on one chip */
/*-----------------------------------------------------------------------
* NAND-FLASH stuff
*-----------------------------------------------------------------------
*/
#undef CFG_NAND_LEGACY
/* NAND debugging */
//#define CONFIG_MTD_DEBUG
//#define CONFIG_MTD_DEBUG_VERBOSE 3
#define CFG_NAND_BASE 0xd4000000
#define CFG_MAX_NAND_DEVICE 1 /* Max number of NAND devices */
#define NAND_MAX_CHIPS 1
//#define CONFIG_MTD_NAND_VERIFY_WRITE 1 /* verify all writes!!! */
//#define CFG_NAND_SKIP_BAD_DOT_I 1 /* ".i" read skips bad blocks */
#define CONFIG_JFFS2_NAND 1 /* jffs2 on nand support */
#define NAND_CACHE_PAGES 16 /* size of nand cache in 512 bytes pages */
#define NAND_ALLOW_ERASE_ALL 1
/*
* JFFS2 partitions
*
*/
/* No command line, one static partition */
//#undef CONFIG_JFFS2_CMDLINE
//#define CONFIG_JFFS2_DEV "nand0"
//#define CONFIG_JFFS2_PART_SIZE 0xFFFFFFFF
//#define CONFIG_JFFS2_PART_OFFSET 0x00060000
/* mtdparts command line support */
/* Note: fake mtd_id used, no linux mtd map file */
#define CONFIG_JFFS2_CMDLINE
#define MTDIDS_DEFAULT "nand0=laze-0"
//#define MTDPARTS_DEFAULT "mtdparts=laze-0:256k(uboot),128k(env),-(jffs2)"
#define MTDPARTS_DEFAULT "mtdparts=laze-0:7168k(Logical),-(JFFS2)"
/*
* SHARP SL NAND logical partition
*/
#define NAND_LOGICAL 1
#define NAND_LOGICAL_SIZE 0x700000
/*
* Environment
*/
#define CFG_ENV_IS_IN_NAND 1
#define CFG_ENV_OFFSET 0x40000
//#define CFG_ENV_OFFSET_REDUND 0x44000
#define CFG_ENV_SIZE 0x20000
#endif /* __CONFIG_H */