library std;
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
use ieee.std_logic_textio.all;
use ieee.numeric_std.all;
use std.textio.all;
entity mux is
port (
mux_sel : in std_logic_vector(1 downto 0);
a,b,c : in std_logic_vector(7 downto 0);
mux_out : out std_logic_vector(7 downto 0)
);
end entity;
architecture struct of mux is
begin
process( mux_sel,a,b,c )
begin
case mux_sel is
when "00" => mux_out <= a;
when "01" => mux_out <= b;
when "10" => mux_out <= c;
when others => mux_out <= c;
end case;
end process;
end architecture;