Someone

module oc_trigger(in,reset,out);
	input in;
	input reset;
	output out;
	reg out;
	integer tmp;
	initial tmp = 0;
	
	always @( posedge in or posedge reset ) begin
			if ( reset ) begin
			tmp=0;
			end
			else if (!reset) begin
			tmp=tmp+1;
				if ( tmp >= 4 ) begin
					out=1;
					tmp=4;
				end
				else 
					out=0;
			end
				
		end
endmodule