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#include <linux/pci.h>
#include <linux/kernel.h>
#include <linux/init.h>
#include <linux/delay.h>
#include <linux/mm.h>
#include <asm/danube/danube.h>
#include <asm/danube/irq.h>
#include <asm/addrspace.h>
#include <linux/vmalloc.h>
#define DANUBE_PCI_REG32( addr ) (*(volatile u32 *)(addr))
#undef DANUBE_PCI_TEST
#define DANUBE_PCI_MEM_BASE 0x18000000
#define DANUBE_PCI_MEM_SIZE 0x02000000
#define DANUBE_PCI_IO_BASE 0x1AE00000
#define DANUBE_PCI_IO_SIZE 0x00200000
#define DANUBE_PCI_CFG_BUSNUM_SHF 16
#define DANUBE_PCI_CFG_DEVNUM_SHF 11
#define DANUBE_PCI_CFG_FUNNUM_SHF 8
#define PCI_ACCESS_READ 0
#define PCI_ACCESS_WRITE 1
static int danube_pci_read_config_dword(struct pci_bus *bus, unsigned int devfn, int where, int size, u32 *val);
static int danube_pci_write_config_dword(struct pci_bus *bus, unsigned int devfn, int where, int size, u32 val);
struct pci_ops danube_pci_ops = {
.read = danube_pci_read_config_dword,
.write = danube_pci_write_config_dword
};
static struct resource pci_io_resource = {
.name = "io pci IO space",
.start = DANUBE_PCI_IO_BASE,
.end = DANUBE_PCI_IO_BASE + DANUBE_PCI_IO_SIZE,
.flags = IORESOURCE_IO
};
static struct resource pci_mem_resource = {
.name = "ext pci memory space",
.start = DANUBE_PCI_MEM_BASE,
.end = DANUBE_PCI_MEM_BASE + DANUBE_PCI_MEM_SIZE,
.flags = IORESOURCE_MEM
};
static struct pci_controller danube_pci_controller = {
.pci_ops = &danube_pci_ops,
.mem_resource = &pci_mem_resource,
.mem_offset = 0x00000000UL,
.io_resource = &pci_io_resource,
.io_offset = 0x00000000UL,
};
static u32 danube_pci_mapped_cfg;
static int danube_pci_config_access(unsigned char access_type,
struct pci_bus *bus, unsigned int devfn, unsigned int where, u32 *data){
unsigned int device = PCI_SLOT(devfn);
unsigned int function = PCI_FUNC(devfn);
unsigned long offset;
unsigned long cfg_base;
unsigned long flags;
u32 temp;
/* Danube support slot from 0 to 15 */
/* dev_fn 0&0x68 (AD29) is danube itself */
//if(device != 1)
// return 1;
if((bus->number != 0) || ((devfn & 0xf8) > 0x78) || ((devfn & 0xf8) == 0) || ((devfn & 0xf8) == 0x68)) {
return 1;
}
// DANUBE_PCI_REG32(PCI_CR_CLK_CTRL_REG) &= (~8);
local_irq_save(flags);
cfg_base = danube_pci_mapped_cfg;
cfg_base |= (bus->number << DANUBE_PCI_CFG_BUSNUM_SHF) | (devfn <<
DANUBE_PCI_CFG_FUNNUM_SHF) | (where & ~0x3);
/* setup the lower bits of the 36 bit address */
offset = 0;// (function << 8) | (where & ~0x3);
/* Perform access */
if (access_type == PCI_ACCESS_WRITE) {
#ifdef CONFIG_DANUBE_PCI_HW_SWAP
*(volatile u32 *) (cfg_base ) = swab32(*data);
#else
*(volatile u32 *) (cfg_base ) = *data;
#endif
} else {
*data = *((volatile u32 *)(cfg_base ));
#ifdef CONFIG_DANUBE_PCI_HW_SWAP
*data = swab32 (*data);
#endif
}
// clean possible Master abort
cfg_base = danube_pci_mapped_cfg | (0x0 << DANUBE_PCI_CFG_FUNNUM_SHF) + 4;
temp = *((volatile u32 *) (cfg_base + offset));
#ifdef CONFIG_DANUBE_PCI_HW_SWAP
temp = swab32 (temp);
#endif
cfg_base = danube_pci_mapped_cfg | (0x68 << DANUBE_PCI_CFG_FUNNUM_SHF) + 4;
*(volatile u32 *) (cfg_base + offset) = temp;
local_irq_restore(flags);
if ((*data) == 0xffffffff) {
return 1;
}
return 0;
}
static int danube_pci_read_config_dword(struct pci_bus *bus, unsigned int devfn, int where, int size, u32 *val){
u32 data = 0;
if (danube_pci_config_access(PCI_ACCESS_READ, bus, devfn, where, &data))
return -1;
*val = data;
return PCIBIOS_SUCCESSFUL;
}
static int danube_pci_write_config_dword(struct pci_bus *bus, unsigned int devfn, int where, int size, u32 val){
u32 data = 0;
if (danube_pci_config_access(PCI_ACCESS_WRITE, bus, devfn, where, &data))
return -1;
return PCIBIOS_SUCCESSFUL;
}
int pcibios_plat_dev_init(struct pci_dev *dev){
u8 pin;
dev->irq = 0;
pci_read_config_byte(dev, PCI_INTERRUPT_PIN, &pin);
switch(pin) {
case 0:
break;
case 1:
//PCI_INTA--shared with EBU
//falling edge level triggered:0x4, low level:0xc, rising edge:0x2
(*DANUBE_EBU_PCC_CON) |= 0xc;
(*DANUBE_EBU_PCC_IEN) |= 0x10;
dev->irq = INT_NUM_IM0_IRL22;
pci_write_config_byte(dev, PCI_INTERRUPT_LINE, (u32)dev->irq);
break;
case 2:
case 3:
case 4:
printk ("WARNING: interrupt pin %d not supported yet!\n", pin);
default:
printk ("WARNING: invalid interrupt pin %d\n", pin);
return 1;
}
return 0;
}
static void __init danube_pci_startup (void){
/*initialize the first PCI device--danube itself */
u32 temp_buffer;
/*TODO: trigger reset */
DANUBE_PCI_REG32 (DANUBE_CGU_IFCCR) &= (~(0xf00000));
DANUBE_PCI_REG32 (DANUBE_CGU_IFCCR) |= ((0x800000));
/* PCIS of IF_CLK of CGU : 1 =>PCI Clock output
0 =>clock input
PADsel of PCI_CR of CGU : 1 =>From CGU
: 0 =>From pad
*/
DANUBE_PCI_REG32 (DANUBE_CGU_IFCCR) |= ((1 << 16));
DANUBE_PCI_REG32 (DANUBE_CGU_PCICR) = ((1 << 31) | (1 << 30));
/* prepare GPIO */
/* PCI_RST: P1.5 ALT 01 */
//pliu20060613: start
*DANUBE_GPIO_P1_OUT |= ((1 << 5));
*DANUBE_GPIO_P1_OD |= ((1 << 5));
*DANUBE_GPIO_P1_DIR |= ((1 << 5));
*DANUBE_GPIO_P1_ALTSEL1 &= (~(1 << 5));
*DANUBE_GPIO_P1_ALTSEL0 &= (~(1 << 5));
//pliu20060613: end
/* PCI_REQ1: P1.13 ALT 01 */
/* PCI_GNT1: P1.14 ALT 01 */
*DANUBE_GPIO_P1_DIR &= (~(0x2000));
*DANUBE_GPIO_P1_DIR |= ((0x4000));
*DANUBE_GPIO_P1_ALTSEL1 &= (~(0x6000));
*DANUBE_GPIO_P1_ALTSEL0 |= ((0x6000));
/* PCI_REQ2: P1.15 ALT 10 */
/* PCI_GNT2: P1.7 ALT 10 */
/* enable auto-switching between PCI and EBU */
DANUBE_PCI_REG32 (PCI_CR_CLK_CTRL_REG) = 0xA;
/* busy, i.e. configuration is not done, PCI access has to be retried */
DANUBE_PCI_REG32 (PCI_CR_PCI_MOD_REG) &= (~(1 << 24));
wmb ();
/* BUS Master/IO/MEM access */
DANUBE_PCI_REG32 (PCI_CS_STS_CMD_REG) |= (7);
temp_buffer = DANUBE_PCI_REG32 (PCI_CR_PC_ARB_REG);
/* enable external 2 PCI masters */
temp_buffer &= (~(0xf << 16));
/* enable internal arbiter */
temp_buffer |= (1 << INTERNAL_ARB_ENABLE_BIT);
/* enable internal PCI master reqest */
temp_buffer &= (~(3 << PCI_MASTER0_REQ_MASK_2BITS));
/* enable EBU reqest */
temp_buffer &= (~(3 << PCI_MASTER1_REQ_MASK_2BITS));
/* enable all external masters request */
temp_buffer &= (~(3 << PCI_MASTER2_REQ_MASK_2BITS));
DANUBE_PCI_REG32 (PCI_CR_PC_ARB_REG) = temp_buffer;
wmb ();
/* FPI ==> PCI MEM address mapping */
/* base: 0xb8000000 == > 0x18000000 */
/* size: 8x4M = 32M */
DANUBE_PCI_REG32 (PCI_CR_FCI_ADDR_MAP0_REG) = 0x18000000;
DANUBE_PCI_REG32 (PCI_CR_FCI_ADDR_MAP1_REG) = 0x18400000;
DANUBE_PCI_REG32 (PCI_CR_FCI_ADDR_MAP2_REG) = 0x18800000;
DANUBE_PCI_REG32 (PCI_CR_FCI_ADDR_MAP3_REG) = 0x18c00000;
DANUBE_PCI_REG32 (PCI_CR_FCI_ADDR_MAP4_REG) = 0x19000000;
DANUBE_PCI_REG32 (PCI_CR_FCI_ADDR_MAP5_REG) = 0x19400000;
DANUBE_PCI_REG32 (PCI_CR_FCI_ADDR_MAP6_REG) = 0x19800000;
DANUBE_PCI_REG32 (PCI_CR_FCI_ADDR_MAP7_REG) = 0x19c00000;
/* FPI ==> PCI IO address mapping */
/* base: 0xbAE00000 == > 0xbAE00000 */
/* size: 2M */
DANUBE_PCI_REG32 (PCI_CR_FCI_ADDR_MAP11hg_REG) = 0xbae00000;
/* PCI ==> FPI address mapping */
/* base: 0x0 ==> 0x0 */
/* size: 32M */
/* BAR1 32M map to SDR address */
DANUBE_PCI_REG32 (PCI_CR_BAR11MASK_REG) = 0x0e000008;
DANUBE_PCI_REG32 (PCI_CR_PCI_ADDR_MAP11_REG) = 0x0;
DANUBE_PCI_REG32 (PCI_CS_BASE_ADDR1_REG) = 0x0;
#ifdef CONFIG_DANUBE_PCI_HW_SWAP
/* both TX and RX endian swap are enabled */
DANUBE_PCI_REG32 (PCI_CR_PCI_EOI_REG) |= 3;
wmb ();
#endif
/*TODO: disable BAR2 & BAR3 */
DANUBE_PCI_REG32 (PCI_CR_BAR12MASK_REG) |= 0x80000000;
DANUBE_PCI_REG32 (PCI_CR_BAR13MASK_REG) |= 0x80000000;
/*use 8 dw burse length */
DANUBE_PCI_REG32 (PCI_CR_FCI_BURST_LENGTH_REG) = 0x303;
DANUBE_PCI_REG32 (PCI_CR_PCI_MOD_REG) |= ((1 << 24));
wmb ();
//pliu20060613: start
*DANUBE_GPIO_P1_OUT &= (~(1 << 5));
wmb ();
mdelay (1);
*DANUBE_GPIO_P1_OUT |= (1 << 5);
}
int pcibios_map_irq(const struct pci_dev *dev, u8 slot, u8 pin){
switch (slot) {
case 13:
/* IDSEL = AD29 --> USB Host Controller */
return INT_NUM_IM1_IRL17;
case 14:
/* IDSEL = AD30 --> mini PCI connector */
return INT_NUM_IM2_IRL14;
default:
printk("Warning: no IRQ found for PCI device in slot %d, pin %d\n", slot, pin);
return 0;
}
}
int pcibios_init(void){
printk ("PCI: Probing PCI hardware on host bus 0.\n");
danube_pci_startup ();
// DANUBE_PCI_REG32(PCI_CR_CLK_CTRL_REG) &= (~8);
danube_pci_mapped_cfg = ioremap(0x17000000, 0x800 * 16);
danube_pci_controller.io_map_base = (unsigned long)ioremap(DANUBE_PCI_IO_BASE, DANUBE_PCI_IO_SIZE);
printk("Danube PCI mapped to 0x%08X\n", (unsigned long)danube_pci_controller.io_map_base);
set_io_port_base(danube_pci_controller.io_map_base);
register_pci_controller(&danube_pci_controller);
return 0;
}
arch_initcall(pcibios_init);