vhdl entity formatter

# Format an entity
sub entity {
    my $in = shift;
    my $max_w = 0;
    # discard the "end entity" line
    $in =~ s{^end\s*entity\s*\w+\s*;$}{}m;
    my @in = split /\n/, $in;
    foreach (@in) {
	# change the "entity X is" definition line to "U_X : X"
	$_ =~ s{^entity\s+([^ ]+)\s+is\s*$}{U_$1 : $1};
	# change "X : integer :=" or "X : in std_logic;" line to "X =>"
	$_ =~ s{^\s+(\w+)\s*\:\s*[^;]+;?\s*$}{    $1\t=>};
	# determine the largest length of the generic/signal for fill
	if (length $1 > $max_w) {
	    $max_w = length $1;
	}
	# change "X (" to "X map ("
	$_ =~ s{^\s+(\w+)\s*\(}{  $1 map \(};
    }
    # Reformat generic/signal lines to be filled properly
    my $fmt = '    %-' . $max_w . "s\t=>\t";
    foreach (@in) {
	if (m{=\>$}) {
	    $_ =~ s{^\s+(\w+)\s*=\>}{};
	    $_ = sprintf $fmt, $1;
	}
    }
    $in = join("\n", @in) . "\n";
    # nestle parenthesis where possible
    $in =~ s{^\s+\)\s+;\s*port\s*([^ ]+)\s*\(\s*$}{  ) port $1 (}ms;

    return $in;
}