rendered paste body/*
* Driver for DANUBEASC serial ports
*
* Based on drivers/char/serial.c, by Linus Torvalds, Theodore Ts'o.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; either version 2 of the License, or
* (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
*
* Copyright (C) 2004 Infineon IFAP DC COM CPE
* Copyright (C) 2007 Felix Fietkau <nbd@openwrt.org>
* Copyright (C) 2007 John Crispin <blogic@openwrt.org>
*/
#include <linux/module.h>
#include <linux/errno.h>
#include <linux/signal.h>
#include <linux/sched.h>
#include <linux/interrupt.h>
#include <linux/tty.h>
#include <linux/tty_flip.h>
#include <linux/major.h>
#include <linux/string.h>
#include <linux/fcntl.h>
#include <linux/ptrace.h>
#include <linux/ioport.h>
#include <linux/mm.h>
#include <linux/slab.h>
#include <linux/init.h>
#include <linux/circ_buf.h>
#include <linux/serial.h>
#include <linux/serial_core.h>
#include <linux/console.h>
#include <linux/sysrq.h>
#include <linux/irq.h>
#include <asm/system.h>
#include <asm/io.h>
#include <asm/uaccess.h>
#include <asm/bitops.h>
#include <asm/danube/danube.h>
#include <asm/danube/irq.h>
#include <asm/danube/serial.h>
#define PORT_DANUBEASC 111
#include <linux/serial_core.h>
#define UART_NR 1
#define UART_DUMMY_UER_RX 1
#define SERIAL_DANUBEASC_MAJOR TTY_MAJOR
#define CALLOUT_DANUBEASC_MAJOR TTYAUX_MAJOR
#define SERIAL_DANUBEASC_MINOR 64
#define SERIAL_DANUBEASC_NR UART_NR
#define SET_BIT(reg, mask) *reg |= (mask)
#define CLEAR_BIT(reg, mask) *reg &= (~mask)
#define SET_BITFIELD(reg, mask, off, val) \
{*reg &= (~mask); *reg |= (val << off);}
static void danubeasc_tx_chars(struct uart_port *port);
extern void prom_printf(const char * fmt, ...);
static struct uart_port danubeasc_ports[UART_NR];
static struct uart_driver danubeasc_reg;
static unsigned int uartclk = 0;
extern unsigned int danube_get_fpi_hz(void);
static void danubeasc_stop_tx(struct uart_port *port)
{
/* fifo underrun shuts up after firing once */
return;
}
static void danubeasc_start_tx(struct uart_port *port)
{
unsigned long flags;
local_irq_save(flags);
danubeasc_tx_chars(port);
local_irq_restore(flags);
return;
}
static void danubeasc_stop_rx(struct uart_port *port)
{
/* clear the RX enable bit */
*DANUBE_ASC1_WHBSTATE = ASCWHBSTATE_CLRREN;
}
static void danubeasc_enable_ms(struct uart_port *port)
{
/* no modem signals */
return;
}
static void
danubeasc_rx_chars(struct uart_port *port)
{
struct tty_struct *tty = port->info->tty;
unsigned int ch = 0, rsr = 0, fifocnt;
fifocnt = *DANUBE_ASC1_FSTAT & ASCFSTAT_RXFFLMASK;
while (fifocnt--)
{
u8 flag = TTY_NORMAL;
ch = *DANUBE_ASC1_RBUF;
rsr = (*DANUBE_ASC1_STATE & ASCSTATE_ANY) | UART_DUMMY_UER_RX;
tty_flip_buffer_push(tty);
port->icount.rx++;
/*
* Note that the error handling code is
* out of the main execution path
*/
if (rsr & ASCSTATE_ANY) {
if (rsr & ASCSTATE_PE) {
port->icount.parity++;
SET_BIT (DANUBE_ASC1_WHBSTATE, ASCWHBSTATE_CLRPE);
} else if (rsr & ASCSTATE_FE) {
port->icount.frame++;
SET_BIT (DANUBE_ASC1_WHBSTATE, ASCWHBSTATE_CLRFE);
}
if (rsr & ASCSTATE_ROE) {
port->icount.overrun++;
SET_BIT (DANUBE_ASC1_WHBSTATE, ASCWHBSTATE_CLRROE);
}
rsr &= port->read_status_mask;
if (rsr & ASCSTATE_PE)
flag = TTY_PARITY;
else if (rsr & ASCSTATE_FE)
flag = TTY_FRAME;
}
if ((rsr & port->ignore_status_mask) == 0)
tty_insert_flip_char(tty, ch, flag);
if (rsr & ASCSTATE_ROE)
/*
* Overrun is special, since it's reported
* immediately, and doesn't affect the current
* character
*/
tty_insert_flip_char(tty, 0, TTY_OVERRUN);
}
if (ch != 0)
tty_flip_buffer_push(tty);
return;
}
static void danubeasc_tx_chars(struct uart_port *port)
{
struct circ_buf *xmit = &port->info->xmit;
if (uart_tx_stopped(port)) {
danubeasc_stop_tx(port);
return;
}
while(((*DANUBE_ASC1_FSTAT & ASCFSTAT_TXFFLMASK)
>> ASCFSTAT_TXFFLOFF) != DANUBEASC_TXFIFO_FULL)
{
if (port->x_char) {
*DANUBE_ASC1_TBUF = port->x_char;
port->icount.tx++;
port->x_char = 0;
continue;
}
if (uart_circ_empty(xmit))
break;
*DANUBE_ASC1_TBUF = port->info->xmit.buf[port->info->xmit.tail];
xmit->tail = (xmit->tail + 1) & (UART_XMIT_SIZE - 1);
port->icount.tx++;
}
if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS)
uart_write_wakeup(port);
}
#define amazon_writel_masked(a,b,c) writel((readl(((u32*)(a))) & ~b) | (c & b), ((u32*)(a)))
static irqreturn_t danubeasc_tx_int(int irq, void *port)
{
// printk("%s:%s[%d]\n", __FILE__, __func__, __LINE__);
writel(ASC_IRNCR_TIR, DANUBE_ASC1 + 0x00F8);
danubeasc_start_tx(port);
amazon_writel_masked(DANUBE_ASC1+ 0x0014,
(DANUBE_ASC1_WHBSTATE_CLRPE | DANUBE_ASC1_WHBSTATE_CLRFE | DANUBE_ASC1_WHBSTATE_CLRROE),
(DANUBE_ASC1_WHBSTATE_CLRPE | DANUBE_ASC1_WHBSTATE_CLRFE | DANUBE_ASC1_WHBSTATE_CLRROE));
return IRQ_HANDLED;
}
static irqreturn_t danubeasc_er_int(int irq, void *port)
{
/* clear any pending interrupts */
SET_BIT (DANUBE_ASC1_WHBSTATE, ASCWHBSTATE_CLRPE);
SET_BIT (DANUBE_ASC1_WHBSTATE, ASCWHBSTATE_CLRFE);
SET_BIT (DANUBE_ASC1_WHBSTATE, ASCWHBSTATE_CLRROE);
return IRQ_HANDLED;
}
static irqreturn_t danubeasc_rx_int(int irq, void *port)
{
*(DANUBE_ASC1_IRNCR) = ASC_IRNCR_RIR;
danubeasc_rx_chars((struct uart_port *) port);
return IRQ_HANDLED;
}
static u_int danubeasc_tx_empty(struct uart_port *port)
{
int status;
/*
* FSTAT tells exactly how many bytes are in the FIFO.
* The question is whether we really need to wait for all
* 16 bytes to be transmitted before reporting that the
* transmitter is empty.
*/
status = *DANUBE_ASC1_FSTAT & ASCFSTAT_TXFFLMASK;
return status ? 0 : TIOCSER_TEMT;
}
static u_int danubeasc_get_mctrl(struct uart_port *port)
{
/* no modem control signals - the readme says to pretend all are set */
return TIOCM_CTS | TIOCM_CAR | TIOCM_DSR;
}
static void danubeasc_set_mctrl(struct uart_port *port, u_int mctrl)
{
/* no modem control - just return */
return;
}
static void danubeasc_break_ctl(struct uart_port *port, int break_state)
{
/* no way to send a break */
return;
}
static void danubeasc1_hw_init(void)
{
u32 con;
/* this setup was probably already done in ROM/u-boot */
/* ASC and GPIO Port 1 bits 3 and 4 share the same pins
* TODO: GPIO pins
*/
/* set up the CLC */
CLEAR_BIT (DANUBE_ASC1_CLC, DANUBE_ASC1_CLC_DISS);
SET_BITFIELD (DANUBE_ASC1_CLC, ASCCLC_RMCMASK, ASCCLC_RMCOFFSET, 1);
/* asynchronous mode */
con = ASCCON_M_8ASYNC;
/* set error signals - framing and overrun */
con |= ASCCON_FEN;
con |= ASCCON_TOEN;
con |= ASCCON_ROEN;
/* choose the line - there's only one */
*DANUBE_ASC1_PISEL = 0;
*DANUBE_ASC1_TXFCON =
(((DANUBEASC_TXFIFO_FL << ASCTXFCON_TXFITLOFF) &
ASCTXFCON_TXFITLMASK) | ASCTXFCON_TXFEN | ASCTXFCON_TXFFLU);
*DANUBE_ASC1_RXFCON =
(((DANUBEASC_RXFIFO_FL << ASCRXFCON_RXFITLOFF) &
ASCRXFCON_RXFITLMASK) | ASCRXFCON_RXFEN | ASCRXFCON_RXFFLU);
wmb ();
SET_BIT (DANUBE_ASC1_CON, con);
}
static int danubeasc_startup(struct uart_port *port)
{
unsigned long flags;
int retval;
/* this assumes: CON.BRS = CON.FDE = 0 */
if (uartclk == 0)
uartclk = danube_get_fpi_hz();
danubeasc_ports[0].uartclk = uartclk;
danubeasc1_hw_init();
local_irq_save(flags);
printk("%s:%s[%d]\n", __FILE__, __func__, __LINE__);
retval = request_irq(DANUBEASC1_RIR, danubeasc_rx_int, 0, "asc_rx", port);
if (retval){
printk("failed to request danubeasc_rx_int\n");
return retval;
}
printk("%s:%s[%d]\n", __FILE__, __func__, __LINE__);
retval = request_irq(DANUBEASC1_TIR, danubeasc_tx_int, 0, "asc_tx", port);
if (retval){
printk("failed to request danubeasc_tx_int\n");
goto err1;
}
printk("%s:%s[%d]\n", __FILE__, __func__, __LINE__);
retval = request_irq(DANUBEASC1_EIR, danubeasc_er_int, 0, "asc_er", port);
if (retval){
printk("failed to request danubeasc_er_int\n");
goto err2;
}
printk("%s:%s[%d]\n", __FILE__, __func__, __LINE__);
/* enable interrupt mask in peripheral */
/* TODO: */
*DANUBE_ASC1_IRNREN = 7;
printk("%s:%s[%d]\n", __FILE__, __func__, __LINE__);
local_irq_restore(flags);
printk("---%s:%s[%d]\n", __FILE__, __func__, __LINE__);
return 0;
err2:
free_irq(DANUBEASC1_TIR, port);
err1:
free_irq(DANUBEASC1_RIR, port);
local_irq_restore(flags);
return retval;
}
static void danubeasc_shutdown(struct uart_port *port)
{
free_irq(DANUBEASC1_RIR, port);
free_irq(DANUBEASC1_TIR, port);
free_irq(DANUBEASC1_EIR, port);
/*
* disable the baudrate generator to disable the ASC
*/
// TODO
// *DANUBE_ASC1_CON = 0;
/* flush and then disable the fifos */
SET_BIT (DANUBE_ASC1_RXFCON, ASCRXFCON_RXFFLU);
CLEAR_BIT (DANUBE_ASC1_RXFCON, ASCRXFCON_RXFEN);
SET_BIT (DANUBE_ASC1_TXFCON, ASCTXFCON_TXFFLU);
CLEAR_BIT (DANUBE_ASC1_TXFCON, ASCTXFCON_TXFEN);
}
static void danubeasc_set_termios(struct uart_port *port, struct ktermios *new, struct ktermios *old)
{
unsigned int cflag;
unsigned int iflag;
unsigned int quot;
unsigned int baud;
unsigned int con = 0;
unsigned long flags;
cflag = new->c_cflag;
iflag = new->c_iflag;
/* byte size and parity */
switch (cflag & CSIZE) {
/* 7 bits are always with parity */
case CS7:
con = ASCCON_M_7ASYNC;
break;
/* the ASC only suports 7 and 8 bits */
case CS5:
case CS6:
default:
con = ASCCON_M_8ASYNC;
break;
}
if (cflag & CSTOPB)
con |= ASCCON_STP;
if (cflag & PARENB) {
if (!(cflag & PARODD))
con &= ~ASCCON_ODD;
else
con |= ASCCON_ODD;
}
port->read_status_mask = ASCSTATE_ROE;
if (iflag & INPCK)
port->read_status_mask |= ASCSTATE_FE | ASCSTATE_PE;
port->ignore_status_mask = 0;
if (iflag & IGNPAR)
port->ignore_status_mask |= ASCSTATE_FE | ASCSTATE_PE;
if (iflag & IGNBRK) {
/*
* If we're ignoring parity and break indicators,
* ignore overruns too (for real raw support).
*/
if (iflag & IGNPAR)
port->ignore_status_mask |= ASCSTATE_ROE;
}
/*
* Ignore all characters if CREAD is not set.
*/
if ((cflag & CREAD) == 0)
port->ignore_status_mask |= UART_DUMMY_UER_RX;
/* set error signals - framing, parity and overrun */
con |= ASCCON_FEN;
con |= ASCCON_TOEN;
/* enable the receiver */
con |= ASCCON_ROEN;
/* block the IRQs */
local_irq_save(flags);
/* set up CON */
SET_BIT (DANUBE_ASC1_CON, con);
/* Set baud rate - take a divider of 2 into account */
baud = uart_get_baud_rate(port, new, old, 0, port->uartclk/16);
quot = uart_get_divisor(port, baud);
quot = quot/2 - 1;
/* disable the baudrate generator */
CLEAR_BIT (DANUBE_ASC1_CON, ASCCON_R);
/* make sure the fractional divider is off */
CLEAR_BIT (DANUBE_ASC1_CON, ASCCON_FDE);
/* set up to use divisor of 2 */
CLEAR_BIT (DANUBE_ASC1_CON, ASCCON_BRS);
/* now we can write the new baudrate into the register */
*DANUBE_ASC1_BG = quot;
/* turn the baudrate generator back on */
SET_BIT (DANUBE_ASC1_CON, ASCCON_R);
/* enable rx */
*DANUBE_ASC1_WHBSTATE = ASCWHBSTATE_SETREN;
local_irq_restore(flags);
}
static const char *danubeasc_type(struct uart_port *port)
{
return port->type == PORT_DANUBEASC ? "DANUBEASC" : NULL;
}
/*
* Release the memory region(s) being used by 'port'
*/
static void danubeasc_release_port(struct uart_port *port)
{
return;
}
/*
* Request the memory region(s) being used by 'port'
*/
static int danubeasc_request_port(struct uart_port *port)
{
return 0;
}
/*
* Configure/autoconfigure the port.
*/
static void danubeasc_config_port(struct uart_port *port, int flags)
{
if (flags & UART_CONFIG_TYPE) {
port->type = PORT_DANUBEASC;
danubeasc_request_port(port);
}
}
/*
* verify the new serial_struct (for TIOCSSERIAL).
*/
static int danubeasc_verify_port(struct uart_port *port, struct serial_struct *ser)
{
int ret = 0;
if (ser->type != PORT_UNKNOWN && ser->type != PORT_DANUBEASC)
ret = -EINVAL;
if (ser->irq < 0 || ser->irq >= NR_IRQS)
ret = -EINVAL;
if (ser->baud_base < 9600)
ret = -EINVAL;
return ret;
}
static struct uart_ops danubeasc_pops = {
.tx_empty = danubeasc_tx_empty,
.set_mctrl = danubeasc_set_mctrl,
.get_mctrl = danubeasc_get_mctrl,
.stop_tx = danubeasc_stop_tx,
.start_tx = danubeasc_start_tx,
.stop_rx = danubeasc_stop_rx,
.enable_ms = danubeasc_enable_ms,
.break_ctl = danubeasc_break_ctl,
.startup = danubeasc_startup,
.shutdown = danubeasc_shutdown,
.set_termios = danubeasc_set_termios,
.type = danubeasc_type,
.release_port = danubeasc_release_port,
.request_port = danubeasc_request_port,
.config_port = danubeasc_config_port,
.verify_port = danubeasc_verify_port,
};
static struct uart_port danubeasc_ports[UART_NR] = {
{
membase: (void *)DANUBE_ASC1,
mapbase: DANUBE_ASC1,
iotype: SERIAL_IO_MEM,
irq: DANUBEASC1_RIR, /* RIR */
uartclk: 0, /* filled in dynamically */
fifosize: 16,
unused: { DANUBEASC1_TIR, DANUBEASC1_EIR}, /* xmit/error/xmit-buffer-empty IRQ */
type: PORT_DANUBEASC,
ops: &danubeasc_pops,
flags: ASYNC_BOOT_AUTOCONF,
},
};
static void danubeasc_console_write(struct console *co, const char *s, u_int count)
{
int i, fifocnt;
unsigned long flags;
local_irq_save(flags);
for (i = 0; i < count;)
{
/* wait until the FIFO is not full */
do
{
fifocnt = (*DANUBE_ASC1_FSTAT & ASCFSTAT_TXFFLMASK)
>> ASCFSTAT_TXFFLOFF;
} while (fifocnt == DANUBEASC_TXFIFO_FULL);
if (s[i] == '\0')
{
break;
}
if (s[i] == '\n')
{
*DANUBE_ASC1_TBUF = '\r';
do
{
fifocnt = (*DANUBE_ASC1_FSTAT &
ASCFSTAT_TXFFLMASK) >>
ASCFSTAT_TXFFLOFF;
} while (fifocnt == DANUBEASC_TXFIFO_FULL);
}
*DANUBE_ASC1_TBUF = s[i];
i++;
}
local_irq_restore(flags);
}
/*
TODO
static void __init
danubeasc_console_get_options(struct uart_port *port, int *baud, int *parity, int *bits)
{
u_int lcr_h;
lcr_h = *DANUBE_ASC1_CON;
if (lcr_h & ASCCON_R) {
u_int quot, div, fdiv, frac;
*parity = 'n';
if ((lcr_h & ASCCON_MODEMASK) == ASCCON_M_7ASYNC ||
(lcr_h & ASCCON_MODEMASK) == ASCCON_M_8ASYNC) {
if (lcr_h & ASCCON_ODD)
*parity = 'o';
else
*parity = 'e';
}
if ((lcr_h & ASCCON_MODEMASK) == ASCCON_M_7ASYNC)
*bits = 7;
else
*bits = 8;
quot = *DANUBE_ASC1_BG + 1;
if (lcr_h & ASCCON_FDE)
{
div = 1;
fdiv = *DANUBE_ASC1_FDV;
if (fdiv == 0)
fdiv = 512;
frac = 512;
}
else
{
div = lcr_h & ASCCON_BRS ? 3 : 2;
fdiv = frac = 1;
}
*baud = frac * (port->uartclk / (div * 512 * 16 * quot));
if (*baud > 1100 && *baud < 2400)
*baud = 1200;
if (*baud > 2300 && *baud < 4800)
*baud = 2400;
if (*baud > 4700 && *baud < 9600)
*baud = 4800;
if (*baud > 9500 && *baud < 19200)
*baud = 9600;
if (*baud > 19000 && *baud < 38400)
*baud = 19200;
if (*baud > 38400 && *baud < 57600)
*baud = 38400;
if (*baud > 57600 && *baud < 115200)
*baud = 57600;
if (*baud > 115200 && *baud < 230400)
*baud = 115200;
}
}
*/
static int __init danubeasc_console_setup(struct console *co, char *options)
{
struct uart_port *port;
int baud = 115200;
int bits = 8;
int parity = 'n';
int flow = 'n';
/* this assumes: CON.BRS = CON.FDE = 0 */
if (uartclk == 0)
uartclk = danube_get_fpi_hz();
co->index = 0;
port = &danubeasc_ports[0];
danubeasc_ports[0].uartclk = uartclk;
danubeasc_ports[0].type = PORT_DANUBEASC;
if (options){
uart_parse_options(options, &baud, &parity, &bits, &flow);
}
return uart_set_options(port, co, baud, parity, bits, flow);
}
static struct uart_driver danubeasc_reg;
static struct console danubeasc_console = {
name: "ttyS",
write: danubeasc_console_write,
device: uart_console_device,
setup: danubeasc_console_setup,
flags: CON_PRINTBUFFER,
index: -1,
data: &danubeasc_reg,
};
static int __init danubeasc_console_init(void)
{
register_console(&danubeasc_console);
return 0;
}
console_initcall(danubeasc_console_init);
static struct uart_driver danubeasc_reg = {
.owner = THIS_MODULE,
.driver_name = "serial",
.dev_name = "ttyS",
.major = TTY_MAJOR,
.minor = 64,
.nr = UART_NR,
.cons = &danubeasc_console,
};
static int __init danubeasc_init(void)
{
unsigned char res;
uart_register_driver(&danubeasc_reg);
res = uart_add_one_port(&danubeasc_reg, &danubeasc_ports[0]);
return res;
}
static void __exit danubeasc_exit(void)
{
uart_unregister_driver(&danubeasc_reg);
}
module_init(danubeasc_init);
module_exit(danubeasc_exit);
MODULE_AUTHOR("openwrt.org");
MODULE_DESCRIPTION("MIPS Danube serial port driver");
MODULE_LICENSE("GPL");