Mine

module keyboard_hw_driver (

	DRV_RESET, 

	KBD_CLK_LINE, KBD_DATA_LINE, 

	DRV_OUT, B);

input KBD_DATA_LINE, KBD_CLK_LINE, DRV_RESET;
output [7:0] DRV_OUT;	// master register for storing keyboard data
output B;

wire KBD_CLK_EF;
reg [7:0] DRV_OUT;
reg [3:0] i; 		// initial value needs to be not equal to 0 through 7. set initial to 10.
reg [7:0] L_SHIFT;
reg [7:0] R_SHIFT;
reg [7:0] CAPS;
reg [7:0] BREAK;
reg B;




// This line is required by Xilinx for FPGA implementation.

//assign KBD_CLK_EF=KBD_CLK_LINE;

IBUF b1(KBD_CLK_EF, KBD_CLK_LINE);

initial begin
	B = 0;
end

// This is the keyboard driver logic (fsm).
always @ (negedge KBD_CLK_EF or posedge DRV_RESET)
begin
	L_SHIFT = 8'b00010010;
	R_SHIFT = 8'b01011001;
	CAPS	  = 8'b01011000;
	BREAK	  = 8'b11110000;	
	
	if(DRV_RESET) 

	begin 

		i=10;
		DRV_OUT=0;
		end
	else begin

		if ((i >= 0) && (i <= 7)) 

		// If i is pointing to a bit of data let us keep it.
		begin
			DRV_OUT = {KBD_DATA_LINE, DRV_OUT[7:1]};
			i = i + 1;
		end
		else if ((i == 8) || (i == 9)) 

		// Otherwise if i is pointing to the parity bit or the stop bit let us ignore it.
		begin
			if ((DRV_OUT == L_SHIFT)||(DRV_OUT == R_SHIFT)||(DRV_OUT == CAPS) || (DRV_OUT == BREAK))
					B = !B;
			i = i + 1;
		end
		else // Else we have a start bit
		begin
			i = 0;
		end 
	end
end

endmodule