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Info about programming the 5i20:
Board wiring (related to programming):
unused <-- 9030 pin 156, GPIO2, bit 8 reg 0x54
FPGA pin 104 = DONE --> 9030 pin 157, GPIO3, bit 11 reg 0x54
FGPA pin 107 = /INIT --> 9030 pin 137, GPIO4, bit 14 reg 0x54
STATUS LED CR11 (low = on) <-- 9030 pin 136, GPIO5, bit 17 reg 0x54
unused <-- 9030 pin 135, GPIO6, bit 20 reg 0x54
FPGA pin 161 = /WRITE <-- 9030 pin 134, GPIO7, but 23 reg 0x54
FPGA pin 106 = /PROGRAM, <-- 9030 pin 94, GPIO8, bit 26 reg 0x54
FPGA pin 155 = CCLK <-> FPGA pin 182 (LCLK 33MHz)
FPGA pin 160 = /CS <-- /LWR (local bus write strobe)
FPGA pin 153 = D0 <-> LAD0 (local data bus)
FPGA pin 146 = D1 <-> LAD1 (local data bus)
FPGA pin 142 = D2 <-> LAD2 (local data bus)
FPGA pin 135 = D3 <-> LAD3 (local data bus)
FPGA pin 126 = D4 <-> LAD4 (local data bus)
FPGA pin 119 = D5 <-> LAD5 (local data bus)
FPGA pin 115 = D6 <-> LAD6 (local data bus)
FPGA pin 108 = D7 <-> LAD7 (local data bus)
Programming sequence:
set /PROGRAM low for 300nS minimum (resets chip and starts clearing memory)
/INIT and DONE go low
set /PROGRAM high
wait for /INIT to go high (100uS max, when done clearing memory)
set /WRITE low
send data bytes (each byte strobes /CS low)
the last few bytes in the file are dummies, which provide the clocks
needed to let the device come out of config mode and begin running
if a CRC error is detected, /INIT will go low
DONE will go high during the dummy bytes at the end of the file
set /WRITE high
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Info about programming the 5i22:
Board wiring (related to programming):
FPGA pin R15 = DONE --> 9054 pin 159, USERI/
FGPA pin U10 = /INIT --> not accessible from the PC
FPGA pin V3 = RD_WR/ <-- pulled low?
FPGA pin E5 = /PROGRAM, <-- 9054 pin 154, USERO/
FPGA pin T15 = CCLK <-> FPGA pin ??? (LCLK 33MHz???)
FPGA pin V2 = /CS <-- /LWR (local bus write strobe)
FPGA pin T12 = D0 <-> LAD0 (local data bus)
FPGA pin R12 = D1 <-> LAD1 (local data bus)
FPGA pin N11 = D2 <-> LAD2 (local data bus)
FPGA pin P11 = D3 <-> LAD3 (local data bus)
FPGA pin U9 = D4 <-> LAD4 (local data bus)
FPGA pin V9 = D5 <-> LAD5 (local data bus)
FPGA pin R7 = D6 <-> LAD6 (local data bus)
FPGA pin T7 = D7 <-> LAD7 (local data bus)
Programming sequence:
set /PROGRAM low for 300nS minimum (resets chip and starts clearing memory)
/INIT and DONE go low (verify that DONE is low, /INIT is inaccessible)
set /PROGRAM high
wait at least 100uS for clearing memory (INIT/ goes high but can't sense it)
set /WRITE low (maybe already pulled low?)
send data bytes (each byte strobes /CS low)
the last few bytes in the file are dummies, which provide the clocks
needed to let the device come out of config mode and begin running
if a CRC error is detected, /INIT will go low (can't tell) and DONE will
not go high.
DONE will go high during the dummy bytes at the end of the file if all is OK
set /WRITE high (or maybe leave alone)
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