ph5

Index: sleep.S===================================================================RCS file: /cvs/linux/kernel26/arch/arm/mach-pxa/sleep.S,vretrieving revision 1.12diff -u -r1.12 sleep.S--- sleep.S	14 Apr 2006 18:40:56 -0000	1.12+++ sleep.S	18 Jun 2006 07:09:18 -0000@@ -244,6 +244,11 @@ 	mov	r0, #PSR_I_BIT | PSR_F_BIT | MODE_SVC	@ set SVC, irqs off 	msr	cpsr_c, r0 +//pH5 debug+	ldr r0, =0x40e00018			@ set GPIO 22 (vibra)+	mov r2, #0x00400000+	str r2, [r0]+ 	ldr	r0, sleep_save_sp		@ stack phys addr 	ldr	r2, =resume_after_mmu		@ its absolute virtual address 	ldmfd	r0, {r3 - r9, sp}		@ CP regs + virt stack ptr@@ -262,6 +267,12 @@ 	mcr 	p15, 0, r6, c3, c0, 0		@ domain ID 	mcr 	p15, 0, r7, c2, c0, 0		@ translation table base addr 	mcr	p15, 0, r8, c1, c1, 0           @ auxiliary control reg++//pH5 debug+	ldr r3, =0x40e00024			@ clear GPIO 22 (vibra)+	mov r4, #0x00400000+	str r4, [r3]+ 	b	resume_turn_on_mmu		@ cache align execution  	.align 5@@ -284,6 +295,12 @@ #ifdef CONFIG_XSCALE_CACHE_ERRATA 	bl	cpu_xscale_proc_init #endif++//pH5 debug+	ldr r2, =0xf2e00024			@ clear GPIO 22 (vibra)+	mov r3, #0x00400000+	str r3, [r2]+ 	ldmfd	sp!, {r2, r3} #ifndef CONFIG_IWMMXT 	mar	acc0, r2, r3