Branching on a set of memory-mapped (read only) flags:
lda flagaddr ; 4
ror ; 2
bcs flag0set ; 2 (or 3 if branch taken)
ror ; 2
bcs flag1set ; 2
... 6 more ror/bcs
; if all the flags were clear, we're at 4+(6*4)=28 cycles here
bcc none_set ; optional
If there are only 2 flags:
bit flagaddr ; 4 cycles, does NOT affect A/X/Y register
bmi flag7set ; 2 cycles. BIT instruction copies bit 7 of flagaddr to N (negative) flag
bvs flag6set ; 2 cycles. BIT copies bit 6 of flagaddr to V (overflow) flag
Also, if all you wanted to test is that neither flag is set, could use a BEQ (branches if flagaddr was zero)
AFP = $D800 ;55296 ASCII to Floating Point (FP) conversion.
FASC = $D8E6 ;55526 FP value to ASCII conversion.
IFP = $D9AA ;55722 Integer to FP conversion
FPI = $D9D2 ;55762 FP to Integer conversion
ZFR0 = $DA44 ;55876 Clear FR0 (set all bytes to 0)
ZF1 = $DA46 ;55878 Clear FR1 (set all bytes to 0) (aka AF1 (De Re))
FSUB = $DA60 ;55904 FP subtract: FR0 = FR0 - FR1
FADD = $DA66 ;55910 FP add: FR0 = FR0 + FR1
FMUL = $DADB ;56027 FP multiply: FR0 = FR0 * FR1
FDIV = $DB28 ;56104 FP divide: FR0 = FR0 / FR1
PLYEVL = $DD40 ;56640 FP polynomial evaluation
FLD0R = $DD89 ;56713 Load FP number into FR0 from 6502 X/Y registers
FLD0P = $DD8D ;56717 Load FP number into FR0 from FLPTR
FLD1R = $DD98 ;56728 Load FP number into FR1 from 6502 X/Y registers
FLD1P = $DD9C ;56732 Load FP number into FR1 from FLPTR
FSTOR = $DDA7 ;56743 Store FP number into 6502 X/Y regs from FR0
FSTOP = $DDAB ;56747 Store FP number from FR0, using FLPTR
FMOVE = $DDB6 ;56758 Move FP number from FR0 into FR1 (FR1 = FR0)
EXP = $DDC0 ;56768 FP base e exponentiation
EXP10 = $DDCC ;56780 FP base 10 exponentiation
LOG = $DECD ;57037 FP natural logarithm
LOG10 = $DED1 ;57041 FP base 10 logarithm