rendered paste body 41540: e3a0320a mov r3, #-1610612736 ; 0xa0000000 # r3 = 0xa0000000 41544: e1a00003 mov r0, r3 # r0 = r3 41548: e3a01034 mov r1, #52 ; 0x34 # for (r1 = 52, 4154c: e3a02000 mov r2, #0 ; 0x0 # csum = 0; r1 > 0; ) {* 41550: e4934004 ldr r4, [r3], #4 # tmp = *r3; r3 += 4; 41554: e2044001 and r4, r4, #1 ; 0x1 # tmp &= 0x1; 41558: e1a04f84 mov r4, r4, lsl #31 # tmp <<= 31; 4155c: e18440a4 orr r4, r4, r4, lsr #1 # tmp |= tmp>>1; 41560: e2511001 subs r1, r1, #1 ; 0x1 # r1--; 41564: e0822004 add r2, r2, r4 # csum += tmp; 41568: 1afffff8 bne 0x41550 # } 4156c: e59f1534 ldr r1, [pc, #1332] ; 0x41aa8 # r1 = 0x40f00000 41570: e5914008 ldr r4, [r1, #8] # r4 = PSPR 41574: e1320004 teq r2, r4 # if (PSPR == csum) 41578: 1a000005 bne 0x41594 # 4157c: e8b00780 ldmia r0!, {r7, r8, r9, sl} # r7 = *(0xa000000) 41580: ee03af10 mcr 15, 0, sl, cr3, cr0, {0} # Domain Access Control (*0xa000000c) 41584: ee029f10 mcr 15, 0, r9, cr2, cr0, {0} # Translation Table Base (*0xa0000008) 41588: ee080f17 mcr 15, 0, r0, cr8, cr7, {0} # Invalidate I&D TLB 4158c: ee018f10 mcr 15, 0, r8, cr1, cr0, {0} # ARM Control Register (*0xa0000004) 41590: e1a0f007 mov pc, r7 # jump to r7 (read from 0xa0000000)