rendered paste body------------------------------------------------------------------------------------
---- Company:
---- Engineer:
----
---- Create Date: 16:35:57 04/25/2007
---- Design Name:
---- Module Name: StorSimulering - Behavioral
---- Project Name:
---- Target Devices:
---- Tool versions:
---- Description:
----
---- Dependencies:
----
---- Revision:
---- Revision 0.01 - File Created
---- Additional Comments:
----
------------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
---- Uncomment the following library declaration if instantiating
---- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
entity StorSimulering is
Port ( clk : in STD_LOGIC;
resetSwitch : in STD_LOGIC;
rxd : in STD_LOGIC;
rts : out STD_LOGIC;
cts : in STD_LOGIC;
txd : out STD_LOGIC;
LEDs : out STD_LOGIC_VECTOR (7 downto 0));
end StorSimulering;
architecture Behavioral of StorSimulering is
component HundraAttaCPLD1 is
Port ( clk : in STD_LOGIC;
internalBus : inout STD_LOGIC_VECTOR (7 downto 0);
addressBus : out STD_LOGIC_VECTOR (11 downto 0);
dataBus : inout STD_LOGIC_VECTOR (7 downto 0);
loadMARHigh : in STD_LOGIC;
loadMARLow : in STD_LOGIC;
loadMBRFromInternalBus : in STD_LOGIC;
loadMBRToInternalBus : in STD_LOGIC;
loadPCLowToBus : in STD_LOGIC;
loadPCHighToBus : in STD_LOGIC;
loadPCLowFromBus : in STD_LOGIC;
loadPCHighFromBus : in STD_LOGIC;
shouldLoadPC : in STD_LOGIC;
incrementPC : in STD_LOGIC;
resetPC : in STD_LOGIC; --från samma knapp som går till resetSwitch i CPLD3
readMemory : in STD_LOGIC;
incrementMAR : in STD_LOGIC;
hoffIsEnabled : in STD_LOGIC;
LEDs : out STD_LOGIC_VECTOR (7 downto 0);
statusBus : in STD_LOGIC_VECTOR (3 downto 0); --från alun
setHoffEnabled : in STD_LOGIC;
resetHoffEnabled : in STD_LOGIC;
loadSRFromInternalBus : in STD_LOGIC;
loadSRToInternalBus : in STD_LOGIC;
loadSRFromAluBus : in STD_LOGIC;
RxRDY : in STD_LOGIC;
TxRDY : in STD_LOGIC;
vesantligastatusbitar : out STD_LOGIC_VECTOR (6 downto 0)--från sr till annat tjaffs (k3), undra varför status -> internalBus finns :/
);
end component;
component HundraAttaCPLD2 is
Port ( clk : in STD_LOGIC;
internalBus : inout STD_LOGIC_VECTOR (7 downto 0);
micromemoryBus : in STD_LOGIC_VECTOR (8 downto 0);
LoadPCLowToBus : out STD_LOGIC;
LoadPCHighToBus : out STD_LOGIC;
LoadPCLowFromBus : out STD_LOGIC;
LoadPCHighFromBus : out STD_LOGIC;
IncrementPC : out STD_LOGIC;
LoadMARHigh : out STD_LOGIC;
LoadMARLow : out STD_LOGIC;
ReadMemory : out STD_LOGIC;
WriteMemory : out STD_LOGIC;
LoadMBRFromInternalBus : out STD_LOGIC;
LoadMBRToInternalBus : out STD_LOGIC;
ResetMPC : out STD_LOGIC;
IncrementMPC : out STD_LOGIC;
LoadMPCMarkerRow : out STD_LOGIC;
LoadMPCOpcodeRow : out STD_LOGIC;
LoadARFromInternalBus : out STD_LOGIC;
LoadARToInternalBus : out STD_LOGIC;
LoadARFromALUBus : out STD_LOGIC;
LoadARToALUBus : out STD_LOGIC;
LoadARFromHelpBus : out STD_LOGIC;
LoadARToHelpBus : out STD_LOGIC;
ALUAdd : out STD_LOGIC ;
LoadSRFromInternalBus : out STD_LOGIC;
LoadSRToInternalBus : out STD_LOGIC;
LoadSRFromALUBus : out STD_LOGIC;
EnableHoff : out STD_LOGIC;
DisableHoff : out STD_LOGIC;
UARTChipSelect : out STD_LOGIC;
UARTWR : out STD_LOGIC ;
UARTRD : out STD_LOGIC ;
JumpInstruction : out STD_LOGIC;
LoadIRFromBus : out STD_LOGIC;
TypeOfJump2 : out STD_LOGIC;
TypeOfJump1 : out STD_LOGIC;
TypeOfJump0 : out STD_LOGIC;
IncrementMAR : out STD_LOGIC;
ALUSub : out STD_LOGIC
);
end component;
component HundraAttaCPLD3 is
Port ( clk : in STD_LOGIC;
internalBus : inout STD_LOGIC_VECTOR (7 downto 0);
loadSRFromAluBus : in STD_LOGIC;
loadARFromInternalBus : in STD_LOGIC;
loadARToInternalBus : in STD_LOGIC;
loadARFromAluBus : in STD_LOGIC;
loadARToAluBus : in STD_LOGIC;
loadARFromHelpBus : in STD_LOGIC;
loadARToHelpBus : in STD_LOGIC;
loadIRFromInternalBus : in STD_LOGIC ;
resetMPC : in STD_LOGIC; --från microminnet
incrementMPC : in STD_LOGIC;
micromemoryBus : out STD_LOGIC_VECTOR (8 downto 0); --till cpld2
loadMPCMarkerRow : in STD_LOGIC;
loadMPCOpcodeRow : in STD_LOGIC;
ALUAdd : in STD_LOGIC;
ALUSub : in STD_LOGIC;
statusBus : out STD_LOGIC_VECTOR (3 downto 0); --från alun
resetSwitch : in STD_LOGIC; --från knapp
status : in STD_LOGIC_VECTOR(6 downto 0); -- från cpld 1 (heter vesantligastatusbitar dar)
jumpInstruction : in STD_LOGIC;
typeOfJump : in STD_LOGIC_VECTOR(2 downto 0);
shouldLoadPC : out STD_LOGIC
);
end component;
component fbart is
port( clk : in std_logic; -- System clock
reset : in std_logic; -- System reset
cs : in std_logic; -- Chip Select
txd : out std_logic; -- Transmitter output
txrdy : out std_logic; -- Transmitter ready for more data
rxd : in std_logic; -- Receiver input
rxrdy : out std_logic; -- Received data ready for reading
wr : in std_logic; -- Write transmitter data
rd : in std_logic; -- Read received data
d : inout std_logic_vector(7 downto 0); -- Data bus
cts : in std_logic; -- Clear To Send
rts : out std_logic); -- Request To Send
end component;
type memtype is array(0 to 2048) of std_logic_vector(7 downto 0);
constant rom : memtype :=
("01100000", "00000000", "00000110", --jmpr
"01001000", "00000000", "00000000", -- JMP 0
"01110000", --rx
"01011000", "00000000", "00001101",
"01001000", "00000000", "00000111",
"01101000",
"01001000", "00000000", "00000000",
--"00001001", "01001000", --LDA med omedelbar adressering och en operand "loop sak"
--"00001001", "01000101",
--"00001001", "01001010",
--"01010000", "00000000", "00000010", -- LDA absolut
others => "00000000");
signal internalBus : STD_LOGIC_VECTOR (7 downto 0);
signal addressBus : STD_LOGIC_VECTOR (11 downto 0);
signal dataBus : STD_LOGIC_VECTOR (7 downto 0);
signal loadMARHigh : STD_LOGIC;
signal loadMARLow : STD_LOGIC;
signal loadMBRFromInternalBus : STD_LOGIC;
signal loadMBRToInternalBus : STD_LOGIC;
signal loadPCLowToBus : STD_LOGIC;
signal loadPCHighToBus : STD_LOGIC;
signal loadPCLowFromBus : STD_LOGIC;
signal loadPCHighFromBus : STD_LOGIC;
signal shouldLoadPC : STD_LOGIC;
signal incrementPC : STD_LOGIC;
signal resetPC : STD_LOGIC; --från samma knapp som går till resetSwitch i CPLD3
signal incrementMAR : STD_LOGIC;
signal hoffIsEnabled : STD_LOGIC;
signal statusBusForAlu : STD_LOGIC_VECTOR (3 downto 0); --från alun
signal setHoffEnabled : STD_LOGIC;
signal resetHoffEnabled : STD_LOGIC;
signal loadSRFromInternalBus : STD_LOGIC;
signal loadSRToInternalBus : STD_LOGIC;
signal loadSRFromAluBus : STD_LOGIC;
signal RxRDY : STD_LOGIC;
signal TxRDY : STD_LOGIC;
signal vesantligastatusbitar : STD_LOGIC_VECTOR (6 downto 0);--från sr till annat tjaffs (k3), undra varför status -> internalBus finns :/
signal micromemoryBus : std_logic_vector(8 downto 0);
signal resetMPC : std_logic;
signal incrementMPC : std_logic;
signal loadMPCMarkerRow : std_logic;
signal loadMPCOpcodeRow : std_logic;
signal loadARFromInternalBus : std_logic;
signal loadARToInternalBus : std_logic;
signal loadARFromALUBus : std_logic;
signal loadARToALUBus : std_logic;
signal loadARFromHelpBus : std_logic;
signal loadARToHelpBus : std_logic;
signal ALUSub : std_logic;
signal ALUAdd : std_logic;
signal UARTChipSelect : std_logic;
signal UARTWR : std_logic;
signal UARTRD : std_logic;
signal JumpInstruction : std_logic;
signal LoadIRFromBus : std_logic;
signal TypeOfJump2 : std_logic;
signal TypeOfJump1 : std_logic;
signal TypeOfJump0 : std_logic;
signal typeofidiothopp : std_logic_vector (2 downto 0);
SIGNAL ReadMemory: std_logic;
SIGNAL WriteMemory: std_logic;
signal foo : std_logic;
signal fbartcs : std_logic;
signal fbartwr : std_logic;
signal fbartrd : std_logic;
signal fbartreset : std_logic;
begin
Ettan : HundraAttaCPLD1
port map (clk => clk,
internalBus => internalBus,
addressBus => addressBus,
dataBus => dataBus,
loadMARHigh => loadMARHigh,
loadMARLow => loadMARLow,
loadMBRFromInternalBus => loadMBRFromInternalBus,
loadMBRToInternalBus => loadMBRToInternalBus,
loadPCLowToBus => loadPCLowToBus,
loadPCHighToBus => loadPCHighToBus,
loadPCLowFromBus => loadPCLowFromBus,
loadPCHighFromBus => loadPcHighFromBus,
shouldLoadPC => shouldLoadPC,
incrementPC => incrementPC,
resetPC => resetSwitch,
readMemory => readMemory,
incrementMAR => incrementMAR,
hoffIsEnabled => hoffIsEnabled,
LEDs => LEDs,
statusBus => statusBusForAlu,
setHoffEnabled => setHoffEnabled,
resetHoffEnabled => resetHoffEnabled,
loadSRFromInternalBus => loadSRFromInternalBus,
loadSRToInternalBus => loadSRToInternalBus,
loadSRFromAluBus => loadSRFromAluBus,
RxRDY => RxRDY,
TxRDY => TxRDY,
vesantligastatusbitar => vesantligastatusbitar);
Tvaan : HundraAttaCPLD2
port map (clk => clk,
internalBus => internalBus,
micromemoryBus => micromemoryBus,
LoadPCLowToBus => loadPCLowToBus,
LoadPCHighToBus => loadPCHighToBus,
LoadPCLowFromBus => loadPCLowFromBus,
LoadPCHighFromBus => loadPCHighFromBus,
IncrementPC => incrementPC,
LoadMARHigh => loadMARHigh,
LoadMARLow => loadMARLow,
ReadMemory => ReadMemory,
WriteMemory => WriteMemory,
LoadMBRFromInternalBus => loadMBRFromInternalBus,
LoadMBRToInternalBus => loadMBRToInternalBus,
ResetMPC => resetMPC,
IncrementMPC => incrementMPC,
LoadMPCMarkerRow => loadMPCMarkerRow,
LoadMPCOpcodeRow => loadMPCOpcodeRow,
LoadARFromInternalBus => loadARFromInternalBus,
LoadARToInternalBus => loadARToInternalBus,
LoadARFromALUBus => loadARFromALUBus,
LoadARToALUBus => loadARToALUBus,
LoadARFromHelpBus => loadARFromHelpBus,
LoadARToHelpBus => loadARToHelpBus,
ALUSub => foo,
ALUAdd => ALUAdd,
LoadSRFromInternalBus => loadSRFromInternalBus,
LoadSRToInternalBus => loadSRToInternalBus,
LoadSRFromALUBus => loadSRFromALUBus,
EnableHoff => setHoffEnabled,
DisableHoff => resetHoffEnabled,
UARTChipSelect => UARTChipSelect,
UARTWR => UARTWR,
UARTRD => UARTRD,
JumpInstruction => JumpInstruction,
LoadIRFromBus => LoadIRFromBus,
TypeOfJump2 => TypeOfJump2,
TypeOfJump1 => TypeOfJump1,
TypeOfJump0 => TypeOfJump0,
IncrementMAR => IncrementMAR);
Trean : HundraAttaCPLD3
port map ( clk => clk,
internalBus => internalBus,
loadSRFromAluBus => loadSRFromAluBus,
loadARFromInternalBus => loadARFromInternalBus,
loadARToInternalBus => loadARToInternalBus,
loadARFromAluBus => loadARFromALUBus,
loadARToAluBus => loadARToALUBus,
loadARFromHelpBus => loadARFromHelpBus,
loadARToHelpBus => loadARToHelpBus,
loadIRFromInternalBus => LoadIRFromBus,
resetMPC => resetMPC,
incrementMPC => incrementMPC,
micromemoryBus => micromemoryBus, --till cpld2
loadMPCMarkerRow => loadMPCMarkerRow,
loadMPCOpcodeRow => loadMPCOpcodeRow,
ALUAdd => ALUAdd,
ALUSub => foo,
statusBus => statusBusForAlu,
resetSwitch => resetSwitch,
status => vesantligastatusbitar, -- från cpld 1 (heter vesantligastatusbitar dar)
jumpInstruction => JumpInstruction,
typeOfJump => typeofidiothopp,
shouldLoadPC => shouldLoadPC);
UART: fbart
port map ( clk => clk, -- System clock
reset => fbartreset, -- System reset
cs => fbartcs, -- Chip Select
txd => txd, -- Transmitter output
txrdy => TxRDY, -- Transmitter ready for more data
rxd => rxd, -- Receiver input
rxrdy => RxRDY, -- Received data ready for reading
wr => fbartwr, -- Write transmitter data
rd => fbartrd, -- Read received data
d => internalBus, -- Data bus
cts => cts, -- Clear To Send
rts => rts);
dataBus <= rom(CONV_INTEGER(addressBus(10 downto 0))) when addressBus(11) ='0' and ReadMemory = '1' else
"ZZZZZZZZ";
typeofidiothopp(2) <= TypeOfJump2;
typeofidiothopp(1) <= TypeOfJump1;
typeofidiothopp(0) <= TypeOfJump0;
fbartreset <= not resetSwitch; --
fbartcs <= not UARTChipSelect; --INTERN!!!!!!!!ALERT typ...
fbartwr <= not UARTWR; --extern
fbartrd <= not UARTRD; --extern
end Behavioral;