All pastes #436791 Raw Edit

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public text v1 · immutable
·published 2007-04-12 18:41 UTC
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Queued messages:
Data TLB Miss Exception (0x1200)!
CPU Register Context:
VEC = 1200  PC  = 80551D9C  MSR = 9032  CR  = 90000005
LR  = 80551B68  CTR = 80591274  XER = 8000197F
R0  = 1  R1  = 80B71060  R2  = 809B0000  R3  = 0
R4  = A  R5  = 80590EB8  R6  = A  R7  = 80940000
R8  = FF000000  R9  = 80000  R10 = 80E15FF0  R11 = 0
R12 = 7710  R13 = FFF31FC8  R14 = 0  R15 = 0
R16 = 0  R17 = 0  R18 = 0  R19 = 0
R20 = 0  R21 = 80A30000  R22 = 809D0000  R23 = 809D0000
R24 = 63  R25 = 809D0000  R26 = 809D0000  R27 = 80A31914
R28 = 80A31914  R29 = 0  R30 = 80B88C34  R31 = 80B67E94

Stack trace:
PC = 80551D9C, SP = 80B71060
Frame 00: SP = 80B71060    RA = 801574EC
.rame 01: SP = 80B71098    RA = 0
*** System received a SegV exception ***
signal= 0xb, code= 0x1200, context= 0x80a0a028
PC = 0x80551d9c, Vector = 0x1200, SP = 0x80b71060