write 1 to reg 2f ( reset host )
poll reg 2f until the 0x01 bit goes to 0
bitset mask 0x01 in register 2c (turns on internal clock)
poll reg 2c until 0x02 bit goes to 1
h# 00 h# 28 cb! \ Not high speed, 1-bit data width, LED off
h# 000b h# 34 cw! \ normal interrupt status en reg
\ Enable: DMA Interrupt, Transfer Complete, CMD Complete
\ Disable: Card Interrupt, Remove, Insert, Read Ready,
\ Write Ready, Block Gap
h# f1ff h# 36 cw! \ error interrupt status en reg
h# 0000 h# 38 cw! \ Normal interrupt status interrupt enable reg
h# 0000 h# 3a cw! \ error interrupt status interrupt enable reg
isr@ drop esr@ drop \ Read interrupt and error status regs, discard results
h# ffff isr! \ Clear all normal interrupts
h# ffff esr! \ Clear all error interrupts