Mine

module adunare(op, mantin, mantout);
    input op;
    input [47:0] mantin;
    output [25:0] mantout;
    reg [25:0]    mantout;

    reg           tmp1;
    reg [24:0]    tmp2;
    
    reg           s1;
    reg           s2;
    reg [24:0]    m1;
    reg [24:0]    m2;
    
    always @(op or mantin) begin
		  m1 = mantin[46:24];
        m2 = mantin[22:0];
        s1 = mantin[47];
        s2 = mantin[23];
 
        if (op) s2 = ~s2; // scadere
		  if (s1==s2) begin
		  	mantout[23:0] = m1 + m2;
			mantout[24] = s1;
			mantout[25] = 0;
		  end
		  else begin
		  	if (m1 > m2) begin
				mantout[23:0] = m1 - m2;
				mantout[24] = s1;
			end
			else begin
				mantout[23:0] = m2 - m1;
				mantout[24] = s2;
			end
			mantout[25] = 1;
		  end
    end
endmodule