Anonymous

module step(clk, hold, step, direction, position, ivelocity);
parameter q=20;
parameter r=12;
input clk, hold;
output step, direction;
input [q-1:0] ivelocity;
output [q+r-1:0] position; reg [q+r-1:0] position;
reg [q-1:0] velocity;

wire [r-1:0] xvelocity = {r{velocity[q-1]}};
wire [q+r-1:0] hvelocity = {xvelocity, velocity};
assign step=position[q-1];
assign direction=velocity[q-1];

always @(posedge clk)
    velocity <= ivelocity;

always @(posedge clk)
    if(!hold)
        position <= position + hvelocity;

endmodule