Timing parameters:
The are five timing parameters which control the output waveform.
No step type uses all five, and only those which will be used are
exported to HAL. In the timing diagrams that follow, they are
identfied by the following numbers:
(1): 'stepgen.n.steplen' = length of the step pulse
(2): 'stepgen.n.stepspace' = minimum space between step pulses
(actual space depends on frequency command, and is infinite
if the frequency command is zero)
(3): 'stepgen.n.dirsetup' = minimum delay after a direction change
and before the next step - may be longer
(4): 'stepgen.n.dirhold' = minimum delay after a step pulse before
a direction change - may be longer
(5): 'stepgen.n.dirdelay' = minimum delay after a step before a
step in the opposite direction - may be longer
Stepping Types:
This module supports a number of stepping types, as follows:
Type 0: Step and Direction
_____ _____ _____
STEP ___________/ \_______/ \_____________/ \___
| | | | | |
Time |--(3)--|-(1)-|--(2)--|-(1)-|--(4)--|-(3)-|-(1)-|
___| |_____________
DIR \___________________________________/
There are two output pins, STEP and DIR. Step pulses appear on
STEP. A positive frequency command results in DIR low, negative
frequency command means DIR high. The minimum period of the
step pulses is 'steplen' + 'stepspace', and the frequency
command is clamped to avoid exceeding these limits. 'steplen'
and 'stepspace' must both be non-zero. 'dirsetup' or 'dirhold'
may be zero, but their sum must be non-zero, to ensure non-zero
low time between the last up step and the first down step.
Type 1: Up/Down
_____ _____
UP __/ \_____/ \________________________________
| | | | |
Time |-(1)-|-(2)-|-(1)-|---(5)---|-(1)-|-(2)-|-(1)-|
|_____| |_____|
DOWN ______________________________/ \_____/ \____
There are two output pins, UP and DOWN. A positive frequency
command results in pulses on UP, negative frequency command
results in pulses on DOWN. The minimum period of the step
pulses is 'steplen' + 'stepspace', and the frequency command
is clamped to avoid exceeding these limits. 'steplen',
'stepspace', and 'dirdelay' must all be non-zero.
Types 2 and higher: State Patterns
STATE |---1---|---2---|---3---|----4----|---3---|---2---|
| | | | | | |
Time |--(1)--|--(1)--|--(1)--|--(1+5)--|--(1)--|--(1)--|
All the remaining stepping types are simply different repeating
patterns on two to five output pins. When a step occurs, the
output pins change to the next (or previous) pattern in the
state listings that follow. The output pins are called 'PhaseA'
thru 'PhaseE'. Timing constraints are obeyed as indicated
in the drawing above. 'steplen' must be non-zero. 'dirdelay'
may be zero. Because stepspace is not used, state based
stepping types can run faster than types 0 and 1.