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library ieee;
use ieee.std_logic_1164.all;

package airLinkMiiPkg is
    component airLinkMii
		generic(width:				positive := 2;
				madd:				std_logic_vector(4 downto 0)
										:= (others => '0')
		);
		port(
			-- Test.
			probe:					out std_logic;

			-- System.
			clk:					in std_logic;
			nReset:					in std_logic;
			nPhyReset:				out std_logic;
			phyClk:					out std_logic;
			
			-- MII interface.
			tx_clk:					out std_logic;
			tx_en:					in std_logic;
			tx_err:					in std_logic;
			txd:					in std_logic_vector(3 downto 0);
			rx_clk:					out std_logic;
			rx_dv:					out std_logic;
			rx_err:					out std_logic;
			rxd:					out std_logic_vector(3 downto 0);
			col:					out std_logic;
			crs:					out std_logic;
			mdc:					in std_logic;
			mdio:					inout std_logic;
			trste:					in std_logic;

			-- GPIO interface.
			gpio:					inout std_logic_vector(3 downto 0);

			-- Synthesizer interface.
			sClk:					out std_logic;
			sData:					out std_logic;
			le:						out std_logic;

			-- Framer interface.
			rxEn:					out std_logic;
			nRxData:				in std_logic;
			txEn:					out std_logic;
			txData:					out std_logic_vector(7 downto 0)
		);
	end component;
end airLinkMiiPkg;


library ieee;
use ieee.std_logic_1164.all;

use work.airLinkMiiCorePkg.all;

entity airLinkMii is
	generic(width:					positive := 2;
			madd:					std_logic_vector(4 downto 0)
										:= (others => '0')
	);
	port(
		-- Test.
		probe:						out std_logic;

		-- System.
		clk:						in std_logic;
		nReset:						in std_logic;
		nPhyReset:					out std_logic;
		phyClk:						out std_logic;
		
		-- MII interface.
		tx_clk:						out std_logic;
		tx_en:						in std_logic;
		tx_err:						in std_logic;
		txd:						in std_logic_vector(3 downto 0);
		rx_clk:						out std_logic;
		rx_dv:						out std_logic;
		rx_err:						out std_logic;
		rxd:						out std_logic_vector(3 downto 0);
		col:						out std_logic;
		crs:						out std_logic;
		mdc:						in std_logic;
		mdio:						inout std_logic;
		trste:						in std_logic;

		-- GPIO interface.
		gpio:						inout std_logic_vector(3 downto 0);

		-- Synthesizer interface.
		sClk:						out std_logic;
		sData:						out std_logic;
		le:							out std_logic;

		-- Framer interface.
		rxEn:						out std_logic;
		nRxData:					in std_logic;
		txEn:						out std_logic;
		txData:						out std_logic_vector(7 downto 0)
	);
end airLinkMii;

architecture rtl of airLinkMii is

	signal reset:					std_logic;
	signal phyClkBuf:				std_logic;

	signal tx_clko:					std_logic;
	signal rx_clko:					std_logic;
	signal rx_dvo:					std_logic;
	signal rx_erro:					std_logic;
	signal rxdo:					std_logic_vector(3 downto 0);
	signal colo:					std_logic;
	signal crso:					std_logic;
	signal mdo:						std_logic;
	signal mdoEn:					std_logic;
	signal miiOe:					std_logic;

	signal gpo:						std_logic_vector(3 downto 0);
	signal gpoEn:					std_logic_vector(3 downto 0);

begin
	reset <= not nReset;
	nPhyReset <= nReset;

	process(clk, reset, phyClkBuf)
	begin
		if(reset = '1') then
			phyClkBuf <= '0';
		elsif(clk'event and (clk = '1')) then
			phyClkBuf <= not phyClkBuf;
		end if;
	end process;

	phyClk <= phyClkBuf;
	
    -- Instantiate the DUT.
	DUT: airLinkMiiCore
	generic map(width => width)
	port map(
		-- Test.
		scanMode => '0',
		probe => probe,

		-- System.
		clk => clk,
		reset => reset,
		
		-- MII interface.
		tx_clk => tx_clko,
		tx_en => tx_en,
		tx_err => tx_err,
		txd => txd,
		rx_clk => rx_clko,
		rx_dv => rx_dvo,
		rx_err => rx_erro,
		rxd => rxdo,
		col => colo,
		crs => crso,
		mdc => mdc,
		mdi => mdio,
		mdo => mdo,
		mdoEn => mdoEn,
		madd => madd,
		trste => trste,
		miiOe => miiOe,

		-- GPIO interface.
		gpi => gpio,
		gpo => gpo,
		gpoEn => gpoEn,
		
		-- Synthesizer interface.
		sClk => sClk,
		sData => sData,
		le => le,

		-- Framer interface.
		rxEn => rxEn,
		nRxData => nRxData,
		txEn => txEn,
		txData => txData
	);

	tx_clk <= tx_clko when(miiOe = '1') else 'Z';
	rx_clk <= rx_clko when(miiOe = '1') else 'Z';
	rx_dv <= rx_dvo when(miiOe = '1') else 'Z';
	rx_err <= rx_erro when(miiOe = '1') else 'Z';
	rxd <= rxdo when(miiOe = '1') else (others => 'Z');
	col <= colo when(miiOe = '1') else 'Z';
	crs <= crso when(miiOe = '1') else 'Z';
	mdio <= mdo when(mdoEn = '1') else 'Z';

	gpioOutputs:
	for i in 0 to 3 generate
		gpio(i) <= gpo(i) when(gpoEn(i) = '1') else 'Z';
	end generate;

end rtl;


configuration cfgRtlOfAirLinkMii of airLinkMii is
    for rtl
		for all: airLinkMiiCore
			use configuration work.cfgRtlOfAirLinkMiiCore;
		end for;
    end for;
end cfgRtlOfAirLinkMii;

configuration cfgAlteraOfAirLinkMii of airLinkMii is
    for rtl
		for all: airLinkMiiCore
			use configuration work.cfgAlteraOfAirLinkMiiCore;
		end for;
    end for;
end cfgAlteraOfAirLinkMii;