Mine

------------ boutreg.vhd -------------

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

--  Uncomment the following lines to use the declarations that are
--  provided for instantiating Xilinx primitive components.
--library UNISIM;
--use UNISIM.VComponents.all;


package boutreg is
    component boutreg is
	generic ( size : integer );
	port (
	    clk : in std_logic;
	    ibus : in std_logic_vector(BusWidth-1 downto 0);
	    obus : out std_logic_vector(BusWidth-1 downto 0);
	    load : in std_logic;
	    read : in std_logic;
	    dout : out std_logic_vector(size -1 downto 0)
	);
    end component boutreg;
end boutreg;

entity boutreg is
    generic ( size : integer );
    port ( clk : in std_logic;
           ibus : in std_logic_vector(31 downto 0);
           obus : out std_logic_vector(31 downto 0);
           load : in std_logic;
           read : in std_logic;
           dout : out std_logic_vector(size -1 downto 0));
end boutreg;

architecture Behavioral of boutreg is
signal oreg : std_logic_vector(size -1 downto 0);


begin

	a_basic_out_reg: process (clk,read,oreg)

	begin
		if clk'event and clk = '1' then
			if load = '1' then
				 oreg <= ibus (size -1 downto 0);
			end if;
		end if; -- clk
		obus <= (others => 'Z');
		if read = '1' then
			obus(size -1 downto 0) <= oreg;
			obus(31 downto size) <= (others => '0');
		end if;		
		dout <= oreg;
	 end process;
end Behavioral;

---------------end of boutreg.vhd ----------------------

---------------top few lines of top.vhd ---------------

library IEEE;
use IEEE.std_logic_1164.all;  -- defines std_logic types
use IEEE.std_logic_ARITH.ALL;
use IEEE.std_logic_UNSIGNED.ALL;

library work;
use work.boutreg.boutreg