Mine

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

entity lab2 is
    Port ( clk : in  STD_LOGIC;
           fc : in  STD_LOGIC;
           rst : in  STD_LOGIC;
           pb : inout  STD_LOGIC_VECTOR (8 downto 0);
           lb : inout  STD_LOGIC_VECTOR (6 downto 0);
           lbs : inout  STD_LOGIC_VECTOR (5 downto 0));
end lab2;

architecture arch_lab2 of lab2 is
	signal cnt : STD_LOGIC_VECTOR (4 downto 0);
	signal zero : STD_LOGIC_VECTOR (5 downto 0);
	signal lbs_check : STD_LOGIC;
begin
	process(clk, rst) is
		begin
			if rst'EVENT and rst = '1' then
				pb <= (others => 0) ;
				lb <= (others => 0) ;
				lbs <= (others => 0) ;
			elsif (clk'EVENT and clk = '1') then
				if fc = '1' then
					cnt <= cnt + 1;
					if zero = "000001" then
						lbs_check <= '1';
					end if
				else
				zero <= zero + '1';   
				-- fc = 0
				if zero > '1' then
					if lbs_check = '1' then
						lbs <= lbs + '1';
						lbs_check <= '0';
					elsif (cnt > 2 and cnt < 5) then
						pb <= pb + '1';
					elsif (cnt > 6 and cnt < 13) then
						lb <= lb + '1';
					end if
					zero <= (others => 0);
					cnt <= (others => 0);
				end if
			end if
	end process
end arch_lab2;