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#ifndef _APPLEONBOARDPCATASHARED_H
#define _APPLEONBOARDPCATASHARED_H

#define kMaxDriveCount          2
#define kMaxChannelCount        2

#define kPrimaryCommandPort     0x1f0
#define kPrimaryControlPort     0x3f4
#define kSecondaryCommandPort   0x170
#define kSecondaryControlPort   0x374

#define kPrimaryIRQ             14
#define kSecondaryIRQ           15

#define kPrimaryChannelID       0
#define kSecondaryChannelID     1

/*
 * Bus master registers are located in I/O space.
 * Register size (bits) indicated in parenthesis.
 */
#define BM_COMMAND              0x00     // (8)  Command register
#define BM_STATUS               0x02     // (8)  Status register
#define BM_PRD_PTR              0x04     // (32) Descriptor table register
#define BM_SEC_OFFSET           8        // offset to channel 1 registers
#define BM_STATUS_INT           0x04     // IDE device asserted its interrupt
#define BM_ADDR_MASK            0xfff0   // BMIBA I/O base address mask

/*
 * PCI Programming Interface register
 */
#define PCI_ATA_PRI_NATIVE_ENABLED     0x01
#define PCI_ATA_PRI_NATIVE_SUPPORTED   0x02
#define PCI_ATA_SEC_NATIVE_ENABLED     0x04
#define PCI_ATA_SEC_NATIVE_SUPPORTED   0x08
#define PCI_ATA_BUS_MASTER_SUPPORTED   0x80