Started : "Synthesize".
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* HDL Compilation *
=========================================================================
Compiling vhdl file "C:/Xilinx/teszt2/teszt2.vhd" in Library work.
Entity <teszt2> compiled.
Entity <teszt2> (Architecture <behavioral>) compiled.
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* HDL Analysis *
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Analyzing Entity <teszt2> (Architecture <behavioral>).
INFO:Xst:1304 - Contents of register <SF_D> in unit <teszt2> never changes during circuit operation. The register is replaced by logic.
Entity <teszt2> analyzed. Unit <teszt2> generated.
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* HDL Synthesis *
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Synthesizing Unit <teszt2>.
Related source file is "C:/Xilinx/teszt2/teszt2.vhd".
INFO:Xst:1799 - State third is never reached in FSM <lcd_state>.
INFO:Xst:1799 - State fourth is never reached in FSM <lcd_state>.
INFO:Xst:1799 - State operational is never reached in FSM <lcd_state>.
Found finite state machine <FSM_0> for signal <lcd_state>.
-----------------------------------------------------------------------
| States | 3 |
| Transitions | 7 |
| Inputs | 4 |
| Outputs | 2 |
| Clock | clock (rising_edge) |
| Power Up State | start |
| Encoding | automatic |
| Implementation | LUT |
-----------------------------------------------------------------------
Found 20-bit comparator less for signal <$n0011> created at line 47.
Found 20-bit adder for signal <$n0018> created at line 37.
Found 1-bit register for signal <allapot>.
Found 25-bit up counter for signal <CTR>.
Summary:
inferred 1 Finite State Machine(s).
inferred 1 Counter(s).
inferred 1 D-type flip-flop(s).
inferred 1 Adder/Subtractor(s).
inferred 1 Comparator(s).
Unit <teszt2> synthesized.
INFO:Xst:1767 - HDL ADVISOR - Resource sharing has identified that some arithmetic operations in this design can share the same physical resources for reduced device utilization. For improved clock frequency you may try to disable resource sharing.
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HDL Synthesis Report
Macro Statistics
# Adders/Subtractors : 1
20-bit adder : 1
# Counters : 1
25-bit up counter : 1
# Registers : 1
1-bit register : 1
# Comparators : 1
20-bit comparator less : 1
=========================================================================
=========================================================================
* Advanced HDL Synthesis *
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Analyzing FSM <FSM_0> for best encoding.
Optimizing FSM <lcd_state> on signal <lcd_state[1:2]> with sequential encoding.
-------------------------
State | Encoding
-------------------------
start | 00
first | 01
second | 10
third | unreached
fourth | unreached
operational | unreached
-------------------------
=========================================================================
Advanced HDL Synthesis Report
Macro Statistics
# FSMs : 1
# Adders/Subtractors : 1
20-bit adder : 1
# Counters : 1
25-bit up counter : 1
# Registers : 3
Flip-Flops : 3
# Comparators : 1
20-bit comparator less : 1
=========================================================================
=========================================================================
* Low Level Synthesis *
=========================================================================
Loading device for application Rf_Device from file '3s500e.nph' in environment C:\Xilinx.
WARNING:Xst:2170 - Unit teszt2 : the following signal(s) form a combinatorial loop: _n0010, _n0009, lcd_counter<0>, LCD_E.
WARNING:Xst:2170 - Unit teszt2 : the following signal(s) form a combinatorial loop: Mcompar__n0011_nor_cyo, lcd_state_FFd1-In, lcd_counter<2>, _n0018<2>, Mcompar__n0011_nor_cyo2, lcd_counter<1>, teszt2__n0018<1>_cyo, _n0018<1>, N6, Mcompar__n0011_nor_cyo3, Mcompar__n0011_nor_cyo1, _n0011, Mcompar__n0011_and_cyo.
WARNING:Xst:2170 - Unit teszt2 : the following signal(s) form a combinatorial loop: lcd_counter<3>, _n0018<3>, lcd_state_FFd2-In, _n0012.
Optimizing unit <teszt2> ...
Mapping all equations...
Building and optimizing final netlist ...
Found area constraint ratio of 100 (+ 5) on block teszt2, actual ratio is 1.
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* Final Report *
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Device utilization summary:
---------------------------
Selected Device : 3s500efg320-5
Number of Slices: 57 out of 4656 1%
Number of Slice Flip Flops: 28 out of 9312 0%
Number of 4 input LUTs: 104 out of 9312 1%
Number of bonded IOBs: 8 out of 232 3%
Number of GCLKs: 1 out of 24 4%
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TIMING REPORT
Clock Information:
------------------
-----------------------------------+------------------------+-------+
Clock Signal | Clock buffer(FF name) | Load |
-----------------------------------+------------------------+-------+
clock | BUFGP | 28 |
-----------------------------------+------------------------+-------+
Timing Summary:
---------------
Speed Grade: -5
Minimum period: 31.746ns (Maximum Frequency: 31.500MHz)
Minimum input arrival time before clock: No path found
Maximum output required time after clock: 35.190ns
Maximum combinational path delay: 6.059ns
=========================================================================
Process "Synthesize" completed successfully