Mine

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

entity teszt2 is
    Port
		(
			led : out STD_LOGIC;
			clock : in STD_LOGIC;
			SF_D : out STD_LOGIC_VECTOR(3 downto 0);
			LCD_E : out STD_LOGIC;
			kapcsolo : in STD_LOGIC
		);
end teszt2;

architecture Behavioral of teszt2 is

signal CTR : STD_LOGIC_VECTOR(24 downto 0);
signal allapot: std_logic;
type lcd_state_enum is ( start, first, second, third, fourth, operational );
signal lcd_state, next_state : lcd_state_enum := start;
signal lcd_counter : STD_LOGIC_VECTOR(19 downto 0) := CONV_STD_LOGIC_VECTOR(0,18);

begin
	assign_next_state : process( clock )
	begin
		if( rising_edge( clock ) ) then
			lcd_state <= next_state;
		end if;
	end process;
	get_next_state : process( lcd_state )
	begin
		lcd_counter <= lcd_counter + 1;
		next_state <= lcd_state;
		LCD_E <= '0';
		case lcd_state is
			when start =>
			   if( lcd_counter = CONV_STD_LOGIC_VECTOR(750000,20) )
				then
					next_state <= first;
					lcd_counter <= CONV_STD_LOGIC_VECTOR(0,20);
				end if;
			when first =>
				if( lcd_counter = CONV_STD_LOGIC_VECTOR(0,20) )
				then
					SF_D <= "0011";
				elsif( lcd_counter < CONV_STD_LOGIC_VECTOR(12,20) )
				then
					LCD_E <= '1';
				elsif( lcd_counter = CONV_STD_LOGIC_VECTOR(205000,20) )
				then
					next_state <= second;
					lcd_counter <= CONV_STD_LOGIC_VECTOR(0,20);
				end if;
			when others =>
				next_state <= lcd_state;
		end case;
	end process;
	process( clock )
	begin
		if rising_edge( clock )
		then
			if (CTR="000000")
			then
				if( allapot = '1' ) then
					allapot <= '0';
				else
					allapot <= '1';
				end if;
			end if;
			CTR <= CTR + 1;
			if (CTR = CONV_STD_LOGIC_VECTOR(25000000,25) )
			then 
				CTR<=CONV_STD_LOGIC_VECTOR(0,25);
			end if;
		end if;
	end process;
	led <= allapot and kapcsolo;
end Behavioral;