library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity teszt2 is
Port
(
led : out STD_LOGIC;
clock : in STD_LOGIC
);
end teszt2;
architecture Behavioral of teszt2 is
signal CTR : STD_LOGIC_VECTOR(5 downto 0);
signal allapot: std_logic;
begin
process( clock )
begin
if clock'event and clock = '1'
then
if (CTR="000000")
then
if( allapot = '1' ) then
led <= '0';
allapot <= '0';
else
led <= '1';
allapot <= '1';
end if;
end if;
CTR <= CTR + "000001";
if (CTR > "100000")
then -- counter reaches 2^13
CTR<="000000";
end if;
end if; -- CLK'event and CLK = '1'
end process;
led <= allapot;
end Behavioral;