Reading .arch file: data/prak06.arch
Reading .net file: data/s27.net
Reading .net file: Parsing Input Block
Reading .net file: Blockname: s27_in_2_
Adding Net: [s27_in_2_, (<OutputPort #0 on InputBlock s27_in_2_ at (0,0).0>)]
Reading .net file: Adding InputBlock [InputBlock s27_in_2_ (0) at (0,0).0]
Reading .net file: Parsing Input Block
Reading .net file: Blockname: s27_in_1_
Adding Net: [s27_in_1_, (<OutputPort #0 on InputBlock s27_in_1_ at (0,0).0>)]
Reading .net file: Adding InputBlock [InputBlock s27_in_1_ (0) at (0,0).0]
Reading .net file: Parsing Input Block
Reading .net file: Blockname: s27_in_3_
Adding Net: [s27_in_3_, (<OutputPort #0 on InputBlock s27_in_3_ at (0,0).0>)]
Reading .net file: Adding InputBlock [InputBlock s27_in_3_ (0) at (0,0).0]
Reading .net file: Parsing Input Block
Reading .net file: Blockname: s27_in_0_
Adding Net: [s27_in_0_, (<OutputPort #0 on InputBlock s27_in_0_ at (0,0).0>)]
Reading .net file: Adding InputBlock [InputBlock s27_in_0_ (0) at (0,0).0]
Reading .net file: Parsing Input Block
Reading .net file: Blockname: clock
Adding Net: [clock, (<OutputPort #0 on InputBlock clock at (0,0).0>)]
Reading .net file: Adding InputBlock [InputBlock clock (0) at (0,0).0]
Reading .net file: Parsing Output Block
Reading .net file: Blockname: out:s27_out
Adding Net: [s27_out, (<InputPort #0 on OutputBlock out:s27_out at (0,0).0>)]
Reading .net file: Adding OutputBlock [OutputBlock out:s27_out (0) at (0,0).0]
Reading .net file: Parsing Logic Block
Reading .net file: Blockname: s27_out
Reading .net file: Parsing pinlist
Reading .net file: Pinlist: [s27_in_3_, n_n41, n_n42, [13], s27_out, open]
Adding ports to existing net: [s27_in_3_, (<InputPort #0 on LogicBlock s27_out at (0,0).0>)]
Adding Net: [n_n41, (<InputPort #1 on LogicBlock s27_out at (0,0).0>)]
Adding Net: [n_n42, (<InputPort #2 on LogicBlock s27_out at (0,0).0>)]
Adding Net: [[13], (<InputPort #3 on LogicBlock s27_out at (0,0).0>)]
Adding ports to existing net: [s27_out, (<OutputPort #4 on LogicBlock s27_out at (0,0).0>)]
Reading .net file: Parsing subblocks
Reading .net file: Subblocks: [s27_out, 0, 1, 2, 3, 4, open]
Reading .net file: Adding LogicBlock [LogicBlock s27_out (0) at (0,0).0]
Reading .net file: Parsing Logic Block
Reading .net file: Blockname: n_n40
Reading .net file: Parsing pinlist
Reading .net file: Pinlist: [s27_in_1_, s27_in_3_, [13], [11], n_n40, clock]
Adding ports to existing net: [s27_in_1_, (<InputPort #0 on LogicBlock n_n40 at (0,0).0>)]
Adding ports to existing net: [s27_in_3_, (<InputPort #1 on LogicBlock n_n40 at (0,0).0>)]
Adding ports to existing net: [[13], (<InputPort #2 on LogicBlock n_n40 at (0,0).0>)]
Adding Net: [[11], (<InputPort #3 on LogicBlock n_n40 at (0,0).0>)]
Adding Net: [n_n40, (<OutputPort #4 on LogicBlock n_n40 at (0,0).0>)]
Adding ports to existing net: [clock, (<InputPort #5 on LogicBlock n_n40 at (0,0).0>)]
Reading .net file: Parsing subblocks
Reading .net file: Subblocks: [n_n40, 0, 1, 2, 3, 4, 5]
Reading .net file: Adding LogicBlock [LogicBlock n_n40 (0) at (0,0).0]
Reading .net file: Parsing Logic Block
Reading .net file: Blockname: n_n41
Reading .net file: Parsing pinlist
Reading .net file: Pinlist: [s27_in_3_, [13], open, open, n_n41, clock]
Adding ports to existing net: [s27_in_3_, (<InputPort #0 on LogicBlock n_n41 at (0,0).0>)]
Adding ports to existing net: [[13], (<InputPort #1 on LogicBlock n_n41 at (0,0).0>)]
Adding ports to existing net: [n_n41, (<OutputPort #4 on LogicBlock n_n41 at (0,0).0>)]
Adding ports to existing net: [clock, (<InputPort #5 on LogicBlock n_n41 at (0,0).0>)]
Reading .net file: Parsing subblocks
Reading .net file: Subblocks: [n_n41, 0, 1, open, open, 4, 5]
Reading .net file: Adding LogicBlock [LogicBlock n_n41 (0) at (0,0).0]
Reading .net file: Parsing Logic Block
Reading .net file: Blockname: n_n42
Reading .net file: Parsing pinlist
Reading .net file: Pinlist: [s27_in_3_, n_n42, [13], open, n_n42, clock]
Adding ports to existing net: [s27_in_3_, (<InputPort #0 on LogicBlock n_n42 at (0,0).0>)]
Adding ports to existing net: [n_n42, (<InputPort #1 on LogicBlock n_n42 at (0,0).0>)]
Adding ports to existing net: [[13], (<InputPort #2 on LogicBlock n_n42 at (0,0).0>)]
Adding ports to existing net: [n_n42, (<OutputPort #4 on LogicBlock n_n42 at (0,0).0>)]
Adding ports to existing net: [clock, (<InputPort #5 on LogicBlock n_n42 at (0,0).0>)]
Reading .net file: Parsing subblocks
Reading .net file: Subblocks: [n_n42, 0, 1, 2, open, 4, 5]
Reading .net file: Adding LogicBlock [LogicBlock n_n42 (0) at (0,0).0]
Reading .net file: Parsing Logic Block
Reading .net file: Blockname: [13]
Reading .net file: Parsing pinlist
Reading .net file: Pinlist: [s27_in_2_, s27_in_0_, n_n40, n_n41, [13], open]
Adding ports to existing net: [s27_in_2_, (<InputPort #0 on LogicBlock [13] at (0,0).0>)]
Adding ports to existing net: [s27_in_0_, (<InputPort #1 on LogicBlock [13] at (0,0).0>)]
Adding ports to existing net: [n_n40, (<InputPort #2 on LogicBlock [13] at (0,0).0>)]
Adding ports to existing net: [n_n41, (<InputPort #3 on LogicBlock [13] at (0,0).0>)]
Adding ports to existing net: [[13], (<OutputPort #4 on LogicBlock [13] at (0,0).0>)]
Reading .net file: Parsing subblocks
Reading .net file: Subblocks: [[13], 0, 1, 2, 3, 4, open]
Reading .net file: Adding LogicBlock [LogicBlock [13] (0) at (0,0).0]
Reading .net file: Parsing Logic Block
Reading .net file: Blockname: [11]
Reading .net file: Parsing pinlist
Reading .net file: Pinlist: [s27_in_2_, n_n40, n_n41, open, [11], open]
Adding ports to existing net: [s27_in_2_, (<InputPort #0 on LogicBlock [11] at (0,0).0>)]
Adding ports to existing net: [n_n40, (<InputPort #1 on LogicBlock [11] at (0,0).0>)]
Adding ports to existing net: [n_n41, (<InputPort #2 on LogicBlock [11] at (0,0).0>)]
Adding ports to existing net: [[11], (<OutputPort #4 on LogicBlock [11] at (0,0).0>)]
Reading .net file: Parsing subblocks
Reading .net file: Subblocks: [[11], 0, 1, 2, open, 4, open]
Reading .net file: Adding LogicBlock [LogicBlock [11] (0) at (0,0).0]
size: 6
Updating blocks from .p File: data/s27.p
Reading .p file: data/s27.p
Reading .p file: Array Size: 3,3
Reading .p file: [Block s27_in_2_ (0) at (2,0).1]
Reading .p file: [Block s27_in_1_ (1) at (4,2).0]
Reading .p file: [Block s27_in_3_ (2) at (3,0).0]
Reading .p file: [Block s27_in_0_ (3) at (2,0).0]
Reading .p file: [Block clock (4) at (0,2).0]
Reading .p file: [Block out:s27_out (5) at (1,0).0]
Reading .p file: [Block s27_out (6) at (1,1).0]
Reading .p file: [Block n_n40 (7) at (3,2).0]
Reading .p file: [Block n_n41 (8) at (3,1).0]
Reading .p file: [Block n_n42 (9) at (1,2).0]
Reading .p file: [Block [13] (10) at (2,1).0]
Reading .p file: [Block [11] (11) at (2,2).0]
Checking .p file for valid coordinates
Checking that all blocks are placed
size: 6
Reading .r file: data/s27.r
net 0 s27_in_2_
input source(2,0).1
input opin(2,0).1
Setting port.net to [s27_in_2_, (<OutputPort #0 on InputBlock s27_in_2_ at (2,0).1>,<InputPort #0 on LogicBlock [13] at (2,1).0>,<InputPort #0 on LogicBlock [11] at (2,2).0>)]
chan x(2,0).0
No Channel found at ChannelX at (2,0). Creating it!
Routing: Adding <Track: 0 of ChannelX at (2,0)> to <OutputPort #0 on InputBlock s27_in_2_ at (2,0).1>
Setting currentVertex to: <Track: 0 of ChannelX at (2,0)>
chan y(1,1).0
No Channel found at ChannelY at (1,1). Creating it!
Routing: Adding <Track: 0 of ChannelY at (1,1)> to <Track: 0 of ChannelX at (2,0)>
Setting currentVertex to: <Track: 0 of ChannelY at (1,1)>
logic ipin(2,1).1
Routing: Adding <InputPort #1 on LogicBlock [13] at (2,1).0> to <Track: 0 of ChannelY at (1,1)>
logic sink(2,1).1
chan y(1,1).0
Setting currentVertex to: <Track: 0 of ChannelY at (1,1)>
chan y(1,2).0
No Channel found at ChannelY at (1,2). Creating it!
Routing: Adding <Track: 0 of ChannelY at (1,2)> to <Track: 0 of ChannelY at (1,1)>
Setting currentVertex to: <Track: 0 of ChannelY at (1,2)>
logic ipin(2,2).1
Routing: Adding <InputPort #1 on LogicBlock [11] at (2,2).0> to <Track: 0 of ChannelY at (1,2)>
loError processing s27_in_3_: channels not connected y x. Skipping net.
gic sink(2,2).1
net 1 s27_in_1_
input source(4,2).0
input opin(4,2).0
Setting port.net to [s27_in_1_, (<OutputPort #0 on InputBlock s27_in_1_ at (4,2).0>,<InputPort #0 on LogicBlock n_n40 at (3,2).0>)]
chan y(3,2).1
No Channel found at ChannelY at (3,2). Creating it!
Routing: Adding <Track: 1 of ChannelY at (3,2)> to <OutputPort #0 on InputBlock s27_in_1_ at (4,2).0>
Setting currentVertex to: <Track: 1 of ChannelY at (3,2)>
logic ipin(3,2).3
Routing: Adding <InputPort #3 on LogicBlock n_n40 at (3,2).0> to <Track: 1 of ChannelY at (3,2)>
logic sink(3,2).3
net 2 s27_in_3_
input source(3,0).0
input opin(3,0).0
Setting port.net to [s27_in_3_, (<OutputPort #0 on InputBlock s27_in_3_ at (3,0).0>,<InputPort #0 on LogicBlock s27_out at (1,1).0>,<InputPort #1 on LogicBlock n_n40 at (3,2).0>,<InputPort #0 on LogicBlock n_n41 at (3,1).0>,<InputPort #0 on LogicBlock n_n42 at (1,2).0>)]
chan x(3,0).0
No Channel found at ChannelX at (3,0). Creating it!
Routing: Adding <Track: 0 of ChannelX at (3,0)> to <OutputPort #0 on InputBlock s27_in_3_ at (3,0).0>
Setting currentVertex to: <Track: 0 of ChannelX at (3,0)>
chan y(3,1).0
No Channel found at ChannelY at (3,1). Creating it!
Routing: Adding <Track: 0 of ChannelY at (3,1)> to <Track: 0 of ChannelX at (3,0)>
Setting currentVertex to: <Track: 0 of ChannelY at (3,1)>
chan y(3,2).0
Routing: Adding <Track: 0 of ChannelY at (3,2)> to <Track: 0 of ChannelY at (3,1)>
Setting currentVertex to: <Track: 0 of ChannelY at (3,2)>
chan x(3,2).0
No Channel found at ChannelX at (3,2). Creating it!
Routing: Adding <Track: 0 of ChannelX at (3,2)> to <Track: 0 of ChannelY at (3,2)>
Setting currentVertex to: <Track: 0 of ChannelX at (3,2)>
chan x(2,2).0
No Channel found at ChannelX at (2,2). Creating it!
Routing: Adding <Track: 0 of ChannelX at (2,2)> to <Track: 0 of ChannelX at (3,2)>
Setting currentVertex to: <Track: 0 of ChannelX at (2,2)>
chan x(1,2).0
No Channel found at ChannelX at (1,2). Creating it!
Routing: Adding <Track: 0 of ChannelX at (1,2)> to <Track: 0 of ChannelX at (2,2)>
Setting currentVertex to: <Track: 0 of ChannelX at (1,2)>
chan y(0,2).0
net 3 s27_in_0_
input source(2,0).0
input opin(2,0).0
Setting port.net to [s27_in_0_, (<OutputPort #0 on InputBlock s27_in_0_ at (2,0).0>,<InputPort #1 on LogicBlock [13] at (2,1).0>)]
chan x(2,0).1
Routing: Adding <Track: 1 of ChannelX at (2,0)> to <OutputPort #0 on InputBlock s27_in_0_ at (2,0).0>
Setting currentVertex to: <Track: 1 of ChannelX at (2,0)>
logic ipin(2,1).0
Routing: Adding <InputPort #0 on LogicBlock [13] at (2,1).0> to <Track: 1 of ChannelX at (2,0)>
logic sink(2,1).0
net 5 s27_out
logic source (1,1).0
logic opin(1,1).0
Setting port.net to [s27_out, (<InputPort #0 on OutputBlock out:s27_out at (1,0).0>,<OutputPort #4 on LogicBlock s27_out at (1,1).0>)]
chan x(1,0).1
net 6 n_n41
logic source (3,1).0
logic opin(3,1).0
Setting port.net to [n_n41, (<InputPort #1 on LogicBlock s27_out at (1,1).0>,<OutputPort #4 on LogicBlock n_n41 at (3,1).0>,<InputPort #3 on LogicBlock [13] at (2,1).0>,<InputPort #2 on LogicBlock [11] at (2,2).0>)]
chan x(3,0).1
net 7 n_n42
logic source (1,2).3
logic opin(1,2).3
Setting port.net to [n_n42, (<InputPort #2 on LogicBlock s27_out at (1,1).0>,<InputPort #1 on LogicBlock n_n42 at (1,2).0>,<OutputPort #4 on LogicBlock n_n42 at (1,2).0>)]
chan x(1,1).1
net 8 [13]
logic source (2,1).3
logic opin(2,1).3
Setting port.net to [[13], (<InputPort #3 on LogicBlock s27_out at (1,1).0>,<InputPort #2 on LogicBlock n_n40 at (3,2).0>,<InputPort #1 on LogicBlock n_n41 at (3,1).0>,<InputPort #2 on LogicBlock n_n42 at (1,2).0>,<OutputPort #4 on LogicBlock [13] at (2,1).0>)]
chan y(2,1).0
No Channel found at ChannelY at (2,1). Creating it!
Routing: Adding <Track: 0 of ChannelY at (2,1)> to <OutputPort #4 on LogicBlock [13] at (2,1).0>
Setting currentVertex to: <Track: 0 of ChannelY at (2,1)>
chan x(2,1).0
No Channel found at ChannelX at (2,1). Creating it!
Routing: Adding <Track: 0 of ChannelX at (2,1)> to <Track: 0 of ChannelY at (2,1)>
Setting currentVertex to: <Track: 0 of ChannelX at (2,1)>
chan x(1,1).0
No Channel found at ChannelX at (1,1). Creating it!
Routing: Adding <Track: 0 of ChannelX at (1,1)> to <Track: 0 of ChannelX at (2,1)>
Setting currentVertex to: <Track: 0 of ChannelX at (1,1)>
logic ipin(1,1).2
Routing: Adding <InputPort #2 on LogicBlock s27_out at (1,1).0> to <Track: 0 of ChannelX at (1,1)>
logic sink(1,1).2
chan x(1,1).0
Setting currentVertex to: <Track: 0 of ChannelX at (1,1)>
logic ipin(1,2).0
Routing: Adding <InputPort #0 on LogicBlock n_n42 at (1,2).0> to <Track: 0 of ChannelX at (1,1)>
logic sink(1,2).0
chan y(2,1).0
Setting currentVertex to: <Track: 0 of ChannelY at (2,1)>
chan x(3,1).0
No Channel found at ChannelX at (3,1). Creating it!
Routing: Adding <Track: 0 of ChannelX at (3,1)> to <Track: 0 of ChannelY at (2,1)>
Setting currentVertex to: <Track: 0 of ChannelX at (3,1)>
logic ipin(3,2).0
Routing: Adding <InputPort #0 on LogicBlock n_n40 at (3,2).0> to <Track: 0 of ChannelX at (3,1)>
logic sink(3,2).0
chan y(2,1).0
Setting currentVertex to: <Track: 0 of ChannelY at (2,1)>
logic ipin(3,1).1
Routing: Adding <InputPort #1 on LogicBlock n_n41 at (3,1).0> to <Track: 0 of ChannelY at (2,1)>
logic sink(3,1).1
net 9 [11]
logic source (2,2).1
logic opin(2,2).1
Setting port.net to [[11], (<InputPort #3 on LogicBlock n_n40 at (3,2).0>,<OutputPort #4 on LogicBlock [11] at (2,2).0>)]
chan y(2,2).0
No Channel found at ChannelY at (2,2). Creating it!
Routing: Adding <Track: 0 of ChannelY at (2,2)> to <OutputPort #4 on LogicBlock [11] at (2,2).0>
Setting currentVertex to: <Track: 0 of ChannelY at (2,2)>
logic ipin(3,2).1
Routing: Adding <InputPort #1 on LogicBlock n_n40 at (3,2).0> to <Track: 0 of ChannelY at (2,2)>
logic sink(3,2).1
net 10 n_n40
logic source (3,2).1
logic opin(3,2).1
Setting port.net to [n_n40, (<OutputPort #4 on LogicBlock n_n40 at (3,2).0>,<InputPort #2 on LogicBlock [13] at (2,1).0>,<InputPort #1 on LogicBlock [11] at (2,2).0>)]
chan x(3,1).1
size: 6
+----------------------------------------+
| FPGA CONTROL OUTPUT |
+----------------------------------------+
*** InputBlocks: ***
[InputBlock s27_in_0_ (3) at (2,0).0]
[InputBlock s27_in_1_ (1) at (4,2).0]
[InputBlock s27_in_2_ (0) at (2,0).1]
[InputBlock s27_in_3_ (2) at (3,0).0]
CLOCK: [InputBlock clock (4) at (0,2).0]
*** Output Blocks: ***
[OutputBlock out:s27_out (5) at (1,0).0]
*** Logic Blocks: ***
[LogicBlock n_n42 (9) at (1,2).0]
[LogicBlock [13] (10) at (2,1).0]
[LogicBlock n_n40 (7) at (3,2).0]
[LogicBlock [11] (11) at (2,2).0]
[LogicBlock n_n41 (8) at (3,1).0]
[LogicBlock s27_out (6) at (1,1).0]
*** Networks: ***
Number of networks: 11
[n_n40, (<OutputPort #4 on LogicBlock n_n40 at (3,2).0>,<InputPort #2 on LogicBlock [13] at (2,1).0>,<InputPort #1 on LogicBlock [11] at (2,2).0>)]
[n_n42, (<InputPort #2 on LogicBlock s27_out at (1,1).0>,<InputPort #1 on LogicBlock n_n42 at (1,2).0>,<OutputPort #4 on LogicBlock n_n42 at (1,2).0>)]
[s27_in_0_, (<OutputPort #0 on InputBlock s27_in_0_ at (2,0).0>,<InputPort #1 on LogicBlock [13] at (2,1).0>)]
[s27_in_3_, (<OutputPort #0 on InputBlock s27_in_3_ at (3,0).0>,<InputPort #0 on LogicBlock s27_out at (1,1).0>,<InputPort #1 on LogicBlock n_n40 at (3,2).0>,<InputPort #0 on LogicBlock n_n41 at (3,1).0>,<InputPort #0 on LogicBlock n_n42 at (1,2).0>)]
[n_n41, (<InputPort #1 on LogicBlock s27_out at (1,1).0>,<OutputPort #4 on LogicBlock n_n41 at (3,1).0>,<InputPort #3 on LogicBlock [13] at (2,1).0>,<InputPort #2 on LogicBlock [11] at (2,2).0>)]
[[13], (<InputPort #3 on LogicBlock s27_out at (1,1).0>,<InputPort #2 on LogicBlock n_n40 at (3,2).0>,<InputPort #1 on LogicBlock n_n41 at (3,1).0>,<InputPort #2 on LogicBlock n_n42 at (1,2).0>,<OutputPort #4 on LogicBlock [13] at (2,1).0>)]
[s27_in_2_, (<OutputPort #0 on InputBlock s27_in_2_ at (2,0).1>,<InputPort #0 on LogicBlock [13] at (2,1).0>,<InputPort #0 on LogicBlock [11] at (2,2).0>)]
[[11], (<InputPort #3 on LogicBlock n_n40 at (3,2).0>,<OutputPort #4 on LogicBlock [11] at (2,2).0>)]
[s27_out, (<InputPort #0 on OutputBlock out:s27_out at (1,0).0>,<OutputPort #4 on LogicBlock s27_out at (1,1).0>)]
[clock, (<OutputPort #0 on InputBlock clock at (0,2).0>,<InputPort #5 on LogicBlock n_n40 at (3,2).0>,<InputPort #5 on LogicBlock n_n41 at (3,1).0>,<InputPort #5 on LogicBlock n_n42 at (1,2).0>)]
[s27_in_1_, (<OutputPort #0 on InputBlock s27_in_1_ at (4,2).0>,<InputPort #0 on LogicBlock n_n40 at (3,2).0>)]
Net 10 (n_n40)
-> OutputPort: <OutputPort #4 on LogicBlock n_n40 at (3,2).0>
Net 7 (n_n42)
-> OutputPort: <OutputPort #4 on LogicBlock n_n42 at (1,2).0>
Net 3 (s27_in_0_)
-> OutputPort: <OutputPort #0 on InputBlock s27_in_0_ at (2,0).0>
-> Track: <Track: 1 of ChannelX at (2,0)>
-> InputPort: <InputPort #0 on LogicBlock [13] at (2,1).0>
Net 2 (s27_in_3_)
-> OutputPort: <OutputPort #0 on InputBlock s27_in_3_ at (3,0).0>
-> Track: <Track: 0 of ChannelX at (3,0)>
-> Track: <Track: 0 of ChannelY at (3,1)>
-> Track: <Track: 0 of ChannelY at (3,2)>
-> Track: <Track: 0 of ChannelX at (3,2)>
-> Track: <Track: 0 of ChannelX at (2,2)>
-> Track: <Track: 0 of ChannelX at (1,2)>
Net 6 (n_n41)
-> OutputPort: <OutputPort #4 on LogicBlock n_n41 at (3,1).0>
Net 8 ([13])
-> OutputPort: <OutputPort #4 on LogicBlock [13] at (2,1).0>
-> Track: <Track: 0 of ChannelY at (2,1)>
-> Track: <Track: 0 of ChannelX at (2,1)>
-> Track: <Track: 0 of ChannelX at (1,1)>
-> InputPort: <InputPort #2 on LogicBlock s27_out at (1,1).0>
-> InputPort: <InputPort #0 on LogicBlock n_n42 at (1,2).0>
-> Track: <Track: 0 of ChannelX at (3,1)>
-> InputPort: <InputPort #0 on LogicBlock n_n40 at (3,2).0>
-> InputPort: <InputPort #1 on LogicBlock n_n41 at (3,1).0>
Net 0 (s27_in_2_)
-> OutputPort: <OutputPort #0 on InputBlock s27_in_2_ at (2,0).1>
-> Track: <Track: 0 of ChannelX at (2,0)>
-> Track: <Track: 0 of ChannelY at (1,1)>
-> InputPort: <InputPort #1 on LogicBlock [13] at (2,1).0>
-> Track: <Track: 0 of ChannelY at (1,2)>
-> InputPort: <InputPort #1 on LogicBlock [11] at (2,2).0>
Net 9 ([11])
-> OutputPort: <OutputPort #4 on LogicBlock [11] at (2,2).0>
-> Track: <Track: 0 of ChannelY at (2,2)>
-> InputPort: <InputPort #1 on LogicBlock n_n40 at (3,2).0>
Net 5 (s27_out)
-> OutputPort: <OutputPort #4 on LogicBlock s27_out at (1,1).0>
Net 0 (clock)
-> OutputPort: <OutputPort #0 on InputBlock clock at (0,2).0>
Net 1 (s27_in_1_)
-> OutputPort: <OutputPort #0 on InputBlock s27_in_1_ at (4,2).0>
-> Track: <Track: 1 of ChannelY at (3,2)>
-> InputPort: <InputPort #3 on LogicBlock n_n40 at (3,2).0>
Net 10 (n_n40)
Visiting OutputPort: <OutputPort #4 on LogicBlock n_n40 at (3,2).0>
Adding <OutputPort #4 on LogicBlock n_n40 at (3,2).0> to n_n40
Net 7 (n_n42)
Visiting OutputPort: <OutputPort #4 on LogicBlock n_n42 at (1,2).0>
Adding <OutputPort #4 on LogicBlock n_n42 at (1,2).0> to n_n42
Net 3 (s27_in_0_)
Visiting OutputPort: <OutputPort #0 on InputBlock s27_in_0_ at (2,0).0>
Adding <OutputPort #0 on InputBlock s27_in_0_ at (2,0).0> to s27_in_0_
Adding <InputPort #0 on LogicBlock [13] at (2,1).0> to s27_in_0_
Net 2 (s27_in_3_)
Visiting OutputPort: <OutputPort #0 on InputBlock s27_in_3_ at (3,0).0>
Adding <OutputPort #0 on InputBlock s27_in_3_ at (3,0).0> to s27_in_3_
Net 6 (n_n41)
Visiting OutputPort: <OutputPort #4 on LogicBlock n_n41 at (3,1).0>
Adding <OutputPort #4 on LogicBlock n_n41 at (3,1).0> to n_n41
Net 8 ([13])
Visiting OutputPort: <OutputPort #4 on LogicBlock [13] at (2,1).0>
Adding <OutputPort #4 on LogicBlock [13] at (2,1).0> to [13]
Adding <InputPort #2 on LogicBlock s27_out at (1,1).0> to [13]
Adding <InputPort #0 on LogicBlock n_n42 at (1,2).0> to [13]
Adding <InputPort #0 on LogicBlock n_n40 at (3,2).0> to [13]
Adding <InputPort #1 on LogicBlock n_n41 at (3,1).0> to [13]
Net 0 (s27_in_2_)
Visiting OutputPort: <OutputPort #0 on InputBlock s27_in_2_ at (2,0).1>
Adding <OutputPort #0 on InputBlock s27_in_2_ at (2,0).1> to s27_in_2_
Adding <InputPort #1 on LogicBlock [13] at (2,1).0> to s27_in_2_
Adding <InputPort #1 on LogicBlock [11] at (2,2).0> to s27_in_2_
Net 9 ([11])
Visiting OutputPort: <OutputPort #4 on LogicBlock [11] at (2,2).0>
Adding <OutputPort #4 on LogicBlock [11] at (2,2).0> to [11]
Adding <InputPort #1 on LogicBlock n_n40 at (3,2).0> to [11]
Net 5 (s27_out)
Visiting OutputPort: <OutputPort #4 on LogicBlock s27_out at (1,1).0>
Adding <OutputPort #4 on LogicBlock s27_out at (1,1).0> to s27_out
Net 0 (clock)
Visiting Clock's OutputPort
Net 1 (s27_in_1_)
Visiting OutputPort: <OutputPort #0 on InputBlock s27_in_1_ at (4,2).0>
Adding <OutputPort #0 on InputBlock s27_in_1_ at (4,2).0> to s27_in_1_
Adding <InputPort #3 on LogicBlock n_n40 at (3,2).0> to s27_in_1_
Error processing s27_out: invalid chan x(1,0).1. Skipping net.
Error processing n_n41: invalid chan x(3,0).1. Skipping net.
Error processing n_n42: invalid chan x(1,1).1. Skipping net.
Error processing n_n40: invalid chan x(3,1).1. Skipping net.