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#2112434 ·published 2012-02-08 14:39 UTC
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library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use ieee.numeric_std.all;

entity hex_to_bcd is
	port (
		CLK_in:		in std_logic;
		INPUT:	in	std_logic_vector( 15 downto 0 );
		BCD_OUTPUT:		out std_logic_vector ( 18 downto 0 ));
end hex_to_bcd;

architecture Behavioral of hex_to_bcd is
begin
	Process (CLK_in, INPUT)
		variable temp: unsigned (34 downto 0);
	begin
		if (rising_edge(CLK_in)) then
			for i in 0 to 34 loop
				temp(i) := '0';
			end loop;
			temp(18 downto 3) := unsigned(INPUT);
		 	for i in 0 to 12 loop
				if temp(19 downto 16) > "0100" then	
					temp(19 downto 16) := temp(19 downto 16) + "0011";
				end if;
				if temp(23 downto 20) > "0100" then	
					temp(23 downto 20) := temp(23 downto 20) + "0011";
				end if;
				if temp(27 downto 24) > "0100" then	
					temp(27 downto 24) := temp(27 downto 24) + "0011";
				end if;
				if temp(31 downto 28) > "0100" then	
					temp(31 downto 28) :=  temp(31 downto 28) + "0011";
				end if;
					temp(34 downto 1) := temp(33 downto 0);
			end loop;
			BCD_OUTPUT <= std_logic_vector(temp(34 downto 16));
		end if;
	end process;
end Behavioral;