Mine

library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;

entity clockmanager is
	port(
		clk : in std_logic;
		wave0 : out std_logic;
		wave1 : out std_logic;
		wave2 : out std_logic;
		wave3 : out std_logic
	);
end entity clockmanager;

architecture logic of clockmanager is
	signal count : integer := 0;
begin
	process(clk)
	begin
		if count < 8 then
			wave0 <= '1';
			wave1 <= '0';
			wave2 <= '0';
			wave3 <= '0';
			count <= count + 1;
		elsif count > 7 and count < 14 then
			wave0 <= '0';
			wave1 <= '1';
			wave2 <= '0';
			wave3 <= '0';
			count <= count + 1;
		elsif count > 13 and count < 21 then
			wave0 <= '0';
			wave1 <= '0';
			wave2 <= '1';
			wave3 <= '0';
			count <= count + 1;
		elsif count > 20 and count < 26 then
			wave0 <= '0';
			wave1 <= '0';
			wave2 <= '0';
			wave3 <= '1';
			count <= count + 1;
		else
			wave0 <= '0';
			wave1 <= '0';
			wave2 <= '0';
			wave3 <= '1';
			count <= 0;
		end if;
	end process;
	
end architecture logic;