Anonymous

-----------------------------------------------------------------------
-- low-pass filter
------------------------------------------------------------------------

architecture lowpass of fir is

  -- The following line is probably needed to avoid a warning
  -- from PrecisionRTL that signals could be implemented using
  -- memory arrays.  If your main signals have different names,
  -- then make the appropriate changes to tap, prod, and sum.
  --attribute logic_block of tap, prod, sum : signal is true;

signal taps : word_vector(0 to 17);
signal prods : word_vector(1 to 17);
signal sums : word_vector(2 to 17);
  
begin

  tapsProc: process(clk)
    begin
      if (rising_edge(clk)) then
        for i in 1 to 17 loop
          taps(i) <= taps(i - 1);      
        end loop;  
      end if;
  end process;
      
  prodGenerator: for i in 1 to 17 generate
    prods(i) <= mult(taps(i), lpcoef(i));
  end generate;

  sums(2) <= prods(1) + prods(2);
  sumGenerator:  for i in 3 to 17 generate
    sums(i) <= sums(i-1) + prods(i);
  end generate;

  o_data <= sums(17);
  
end architecture;