Untitled

//program to do a simple AND statement
module 	program1 (a,b,z);
input 	a,b;
output 	z;
wire	w1;
assign w1 = a & b;
assign z  = w1;
endmodule

//D Flip Flop with Asynchronous Reset of 0
module DFlipFlopAsynch(D,clk,reset,Q);
input	D,clk,reset;
output	Q;
reg		Q;

always @ (posedge clk or negedge reset)
if (~reset) begin
	Q <= 1'b0;	//flash with bit0
end
else begin
	Q <= D;
end
endmodule

//Slow Clock Module
module Clock50to1Hz(input FastClock, output reg SlowClock);
reg [25:0]R;

always @(posedge FastClock)
begin
	if (R<25000000)
		R <= R+26'b1;
	else
		begin
			SlowClock <= ~SlowClock;
			R <= 0;
		end
	end
endmodule

//mux that will be used to stall the Shift register
module mux2to1 (a, b, select, z);
input 	a;
input 	b;
input 	select;
output	z;
reg 	z;

always @(select or a or b)
begin: MUX
	if (select == 1'b0) begin
		z = a;
	end else begin
		z = b;
	end
end
endmodule


//Shift Register Test
module Test (SW, LEDR, LEDG, KEY, CLOCK_50);
input 	[17:0]SW;
input 	CLOCK_50;
input 	[3:0]KEY;
output	[17:0]LEDR;
output  [8:0]LEDG;
wire	SlowClock;
wire	Q1,Q2,Q3,Q4,Q5,Q6,Q7,Q8;	
wire    result;

mux2to1(1'b0,SlowClock, SW[1], result);	

Clock50to1Hz(CLOCK_50,SlowClock);	//use our SlowClock to drive the clock input to all DFFs when selected

assign LEDG[0] = result;

	DFlipFlopAsynch( (SW[0] | (Q8 & ~SW[2])) ,result,KEY[0],Q1); 	//circular shift register input is SW[0] OR Q8 so that at the end it will keep circulating
	assign LEDR[0] = Q1;

	DFlipFlopAsynch(Q1,result,KEY[0],Q2);
	assign LEDR[1] = Q2;

	DFlipFlopAsynch(Q2,result,KEY[0],Q3);
	assign LEDR[2] = Q3;

	DFlipFlopAsynch(Q3,result,KEY[0],Q4);
	assign LEDR[3] = Q4;

	DFlipFlopAsynch(Q4,result,KEY[0],Q5);
	assign LEDR[4] = Q5;

	DFlipFlopAsynch(Q5,result,KEY[0],Q6);
	assign LEDR[5] = Q6;

	DFlipFlopAsynch(Q6,result,KEY[0],Q7);
	assign LEDR[6] = Q7;

	DFlipFlopAsynch(Q7,result,KEY[0],Q8);
	assign LEDR[7] = Q8;

endmodule