lautriv

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;

entity transc8 is
Port(
	DA,DB : inout  STD_LOGIC_VECTOR (7 downto 0);
	DIR : in  STD_LOGIC 
  );
end transc8;

architecture transc8_A of transc8 is
begin
	process (DIR)
	begin
		if (DIR='1') then 
		DA <= (DB);
		else 
		DB <= (DA);
		end if;
	end process;
end transc8_A;