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entity question3 is
    Port ( x : in  STD_LOGIC;
           y : in  STD_LOGIC;
           z : in  STD_LOGIC;
           res1 : out  STD_LOGIC;
           res2 : out  STD_LOGIC);
end question3;

architecture Behavioral of question3 is
signal sig_s1, sig_s2:std_logic;
begin
	proc1:process (x,y,z) is
		variable var_s1, var_s2:std_logic;
		begin 
			L1: var_s1 := x and y;
			L2: var_s2 := var_s1 xor z;
			L3: res1 <=  var_s1 nand var_s2;
		end process proc1;
	proc2:process (x,y,z) is
		begin
			L1: sig_s1 <= x and y;
			L2: sig_s2 <= sig_s1 xor z;
			L3: res2 <= sig_s1 nand sig_s2;
		end process proc2;
end Behavioral;