Someone

module s3(o, y, x1, x2, os);
     output o, y;
     input x1,x2,os;
     wire t1, t2, nos, z1,z2,z3, z4, a1, a2, a3;
     
     not(t1, x1);
     not(t2, x2);
     not(nos, os);

and(z1, x1, t2, nos);
and(z2, t1, x2, nos);
and(z3, t1, t2, os);
and(z4, x1, x2, os);
or(y, z1, z2, z3, z4);

and(a1, x1, x2);
and(a2, t1, x2, os);
and(a3, x1, t2, os);
or(o, a1, a2, a3);
endmodule

module neg(y1, y2, y3, x1,x2,x3);
output y1,y2,y3;
input x1, x2, x3;
wire t1, t2, t3, o1,o2,o3, z1, zero, one;


not(z1, x1);
and(zero, z1, x1);   
not(one, zero);


not(t1,x1);
not(t2,x2);
not(t3,x3);

s3 xxx(o1, y3, t3, one, zero);
s3 xxx(o2, y2, t2, zero, o1);
s3 xxx(o3, y1, t1, zero, o2);
endmodule


module main(y1,y2,y3,y4,y5,x1,x2,x3,x4,x5,x6,x7,x8);
     output y1, y2,y3,y4,y5;
     input x1,x2,x3,x4,x5,x6,x7,x8;
	wire z1, zero, o1, o2,o3,o4,o5;

not(z1, x1);
and(zero, z1, x1);   
   
   s3 xxx(o1, y5, x4, x8, zero);
   s3 xxx(o2, y4, x3, x7, o1);
   s3 xxx(o3, y3, x2, x6, o2);
   s3 xxx(y1, y2, x1, x5, o3);
endmodule











module s3(o, y, x1, x2, os);
     output o, y;
     input x1,x2,os;
     wire t1, t2, nos, z1,z2,z3, z4, a1, a2, a3;
     
     not(t1, x1);
     not(t2, x2);
     not(nos, os);

and(z1, x1, t2, nos);
and(z2, t1, x2, nos);
and(z3, t1, t2, os);
and(z4, x1, x2, os);
or(y, z1, z2, z3, z4);

and(a1, x1, x2);
and(a2, t1, x2, os);
and(a3, x1, t2, os);
or(o, a1, a2, a3);
endmodule


//=================================================================================

module neg(y0, y1, y2, y3, y4, y5, y6, y7, y8, x0, x1, x2, x3, x4, x5, x6, x7, x8);
output y0, y1, y2, y3, y4, y5, y6, y7, y8;
input x0, x1, x2, x3, x4, x5, x6, x7, x8;
wire t0, t1, t2, t3, t4,t5,t6,t7,t8, o1,o2,o3,o4,o5,o6,o7,o8,o9, zero, one;


not(z1, x1);
and(zero, z1, x1);   
not(one, zero);


assign t0 = ~x0;
assign t1 = ~x1;
assign t2 = ~x2;
assign t3 = ~x3;
assign t4 = ~x4;
assign t5 = ~x5;
assign t6 = ~x6;
assign t7 = ~x7;
assign t8 = ~x8;

s3 xxx(o1, y8, t8, one, zero);
s3 xxx(o2, y7, t7, zero, o1);
s3 xxx(o3, y6, t6, zero, o2);
s3 xxx(o4, y5, t5, zero, o3);
s3 xxx(o5, y4, t4, zero, o4);
s3 xxx(o6, y3, t3, zero, o5);
s3 xxx(o7, y2, t2, zero, o6);
s3 xxx(o8, y1, t1, zero, o7);
s3 xxx(o9, y0, t0, zero, o8);
endmodule


module main(y0, y1, y2, y3, y4, y5, y6, y7, y8, a0, a1, a2, a3, a4, a5, a6, a7, a8, b0, b1, b2, b3, b4, b5, b6, b7, b8);
     output y0, y1, y2, y3, y4, y5, y6, y7, y8;
     input a0, a1, a2, a3, a4, a5, a6, a7, a8, b0, b1, b2, b3, b4, b5, b6, b7, b8;
	wire z1, zero, o1,o2,o3,o4,o5,o6,o7,o8,o9;

not(z1, x1);
and(zero, z1, x1);   
   
   s3 xxx(o1, y8, a8, b8, zero);
   s3 xxx(o2, y7, a7, b7, o1);
   s3 xxx(o3, y7, a6, b6, o2);
   s3 xxx(o4, y7, a5, b5, o3);
   s3 xxx(o5, y7, a4, b4, o4);
   s3 xxx(o6, y7, a3, b3, o5);
   s3 xxx(o7, y7, a2, b2, o6);
   s3 xxx(o8, y7, a1, b1, o7);
   s3 xxx(o9, y7, a0, b0, o8);
endmodule



module incr(y0, y1, y2, y3, y4, y5, y6, y7, y8, a0, a1, a2, a3, a4, a5, a6, a7, a8);
     output y0, y1, y2, y3, y4, y5, y6, y7, y8;
     input a0, a1, a2, a3, a4, a5, a6, a7, a8;
     wire z1, one, zero, o1,o2,o3,o4,o5,o6,o7,o8,o9;

not(z1, x1);
and(zero, z1, x1);  
or(zero, z1, x1);   
   
   main xxx(y0, y1, y2, y3, y4, y5, y6, y7, y8, a0, a1, a2, a3, a4, a5, a6, a7, a8, zero, zero, zero, zero, zero, zero, zero, zero, one);
endmodule








module s3gs(q, nq, s, c, r);
     output q, nq;
     input s, c, r;


assign q = ~(~(c&s) & nq);
assign nq = ~(~(c&r) & q);


endmodule

module dtri(q, nq, d, c);
     output q, nq;
     input d, c;


assign q = ~(~(c & d) & nq);
assign nq = ~(~(c & ~(c & d)) & q);


endmodule