rendered paste bodymodule part4(SW,KEY,CLOCK_50,LEDR);
input CLOCK_50; //50MHz internal clock
input [2:0] SW; //inputs for characters A-H
input [1:0] KEY; //KEY[1] is button that loads the letter
//KEY[0] is asynchronous reset
output reg [0:0] LEDR; //morse code output
parameter A = 0, B = 1, C = 2, D = 3, E = 4, F = 5, G = 6, H = 7;
parameter patA = 4'b0001, patB = 4'b1110, patC = 4'b1010, patD = 4'b0110,
patE = 4'b0001, patF = 4'b1011, patG = 4'b0100, patH = 4'b1111;
reg [3:0]letterSize; //length of w
reg [3:0]w; //input into the letter symbols shift register
//0 is dot, 1 is dash
wire newPattern;
wire clk;
assign clk = ~KEY[1];
wire resetn;
assign resetn = KEY[0];
always@(posedge clk)
begin
case(SW)
A: begin letterSize = 2;
w = patA; end
B: begin letterSize = 4;
w = patB; end
C: begin letterSize = 4;
w = patC; end
D: begin letterSize = 3;
w = patD; end
E: begin letterSize = 1;
w = patE; end
F: begin letterSize = 4;
w = patF; end
G: begin letterSize = 3;
w = patG; end
H: begin letterSize = 4;
w = patH; end
endcase
end
parameter Default = 0, Dot = 1, Dash = 2;
reg [1:0]nextState = 2'b00;
reg restPeriod = 0;
integer k = 0;
reg [2:0]count = 4;
always @(posedge CLOCK_50) //print morsecode
begin
k = k + 1;
if (clk)
count = 0;
if (!restPeriod)
begin
if (k == 25000000) //0.5 sec
begin
restPeriod = (count < letterSize)? ~restPeriod: restPeriod; //turns restPeriod 1
case (count)
A: if (w[0]) nextState = Dot;
else nextState = Dash;
B: if(w[1]) nextState = Dot;
else nextState = Dash;
C: if(w[2]) nextState = Dot;
else nextState = Dash;
D: if(w[3]) nextState = Dot;
endcase
k = 0;
end
end
else if (restPeriod & (nextState == Dash))
begin
LEDR[0] = (count < letterSize)? 1: 0;
if (k == 75000000) //1.5sec
begin
LEDR[0] = 0;
count = (count < letterSize)? (count +1):count;
k = 0;
restPeriod = ~restPeriod;
end
end
else if (restPeriod & (nextState == Dot))
begin
LEDR[0] = (count < letterSize)? 1: 0;
if (k == 12500000) //0.25 sec
begin
LEDR[0] = 0;
count = (count < letterSize)? (count +1) :count;
k = 0;
restPeriod = ~restPeriod;
end
end
end
endmodule
module Reg (D, Q, clk, resetn);
input clk;
input [1:0]D;
input resetn;
output reg [1:0]Q;
always @ (posedge clk)
if (!resetn)
Q <= 0;
else
Q <= D;
endmodule