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`default_nettype none
//
// de1floppy
//
module de1floppy (
	CLOCK_50,
	
	// from floppy drive
	nINDEX,	nCHANGE, nRDY, nRDATA, nTRK0, nWPROT,
	
	// to floppy drive
	nSEL0, nSEL1, nMTRON, DIR, nSTEP, nWDATA, nWGATE, nSIDE,
	
	// indication
	LEDG, LEDR, HEX0, HEX1, HEX2, HEX3,
	
	// controls
	KEY, SW,
	
	// VGA
	VGA_HS, VGA_VS, VGA_R, VGA_G, VGA_B,
	
	// RS-232
	UART_TXD, UART_RXD
	
	);	// 25:10

input CLOCK_50;

input nINDEX, nCHANGE, nRDY, nRDATA, nTRK0, nWPROT;

output nSEL0, nSEL1, nMTRON, DIR, nSTEP, nWDATA, nWGATE, nSIDE;

output [7:0] LEDG;
output [9:0] LEDR;
output [6:0] HEX0;
output [6:0] HEX1; 
output [6:0] HEX2;
output [6:0] HEX3;
input [3:0] KEY;
input [9:0] SW;
output VGA_HS, VGA_VS;
output [3:0] VGA_R;
output [3:0] VGA_G;
output [3:0] VGA_B;
output 	UART_TXD;
inout	UART_RXD;

// ---------------------------------------------------------------------------------

wire [15:0] addr_out;
wire vma;
wire io;
wire rd;
wire wr;
wire fetch;
wire [7:0] data_in;
wire [7:0] data_out;
wire [7:0] output_port;

wire clk = SW [0] ? counter [23] : clk_25mhz;
wire clk2 = SW [0] ? counter [22] : clk_50mhz;

//
// light 8080
//
light8080 light8080_i (
	.addr_out (addr_out [15:0]),
	
	.intr (1'b0),
	
	.vma (vma),
	.io (io),
	.rd (rd),
	.wr (wr),
	.fetch (fetch),
	
	.data_in (data_in [7:0]),
	.data_out (data_out [7:0]),
	
	.clk (clk),
	.reset (reset)
	
	);

reg io_r;
reg [15:0] addr_r;
always @(posedge (clk & vma)) begin
	io_r <= io;
	addr_r [15:0] <= addr_out [15:0];
end

/*
	Address map
	=================================
	0000 - 0FFF		code & stack memory
	1000 - 1FFF		buffer
*/


/*
assign data_in [7:0] = 	io_r 		? 	io_q [7:0] 	: 
						memsel_r 	? 	mem_q [7:0] : 
										buf_q [7:0];
*/

assign data_in [7:0] = idata [7:0];

reg [7:0] idata;
always @(*) begin
	if (io_r)
		idata [7:0] <= io_q;
	else
		case (addr_r [13:12])
			2'b00:		idata [7:0] <= mem_q [7:0];
			2'b01:		idata [7:0] <= buf_q [7:0];
	//		2'b10:		idata [7:0] <= 8'h76;
	//		2'b11:		idata [7:0] <= 8'h76;
			default:	idata [7:0] <= 8'hff;			
		endcase
end

//
// Memory
//
//wire memclk = clk & memsel & vma & ~io;
wire [7:0] mem_q;
memory memory_i (
	
	.clk (clk),
	
	.reset (reset),
	
	.addr (addr_out [15:0]),
	.vma (vma),
	.rd (rd),
	.wr (wr),
	.io (io),
	.data_in (data_out [7:0]),
	.mem_q (mem_q [7:0]),
	
	);

//
// I/O
//
wire [7:0] io_q;
io io_i (
	.clk (clk),
	.reset (reset),
	
	.addr (addr_out [7:0]),		// only 256 ports
	.vma (vma),
	.rd (rd),
	.wr (wr),
	.io (io),
	.data_in (data_out [7:0]),
	.io_q (io_q [7:0]),

	.led_port (output_port [7:0]),
	.switches_port (SW [7:0]),
	.floppy_input_port ({nINDEX, nCHANGE, nRDY, nRDATA, nTRK0, nWPROT, 2'b0}),
	.floppy_output_port ({nSEL0, nSEL1, nMTRON, DIR, nSTEP, nWDATA, nWGATE, nSIDE}),
	
	.uart_txd (UART_TXD),
	
	.dma (dma),	.fill (fill), .buflen (buflen [7:0])
	
);


//
// Buffer
//
wire fill;
wire dma;
wire [7:0] buf_q;
//wire bufclk = clk & bufsel & vma & ~io;
wire [7:0] buflen;
buffer buffer_i (
	.clk (clk),
	.reset (reset),
	.cpu_addr (addr_out [15:0]),
	.cpu_data_in (data_out [7:0]),
	.buf_q (buf_q [7:0]),
	
	.vma (vma),	.rd (rd), .wr (wr),	.io (io),
	
	.floppy_rdata (nRDATA),
	
	.dma (dma),	.fill (fill), .buflen (buflen [7:0])
		
);


SEG7_LUT_4 hexdisplay (		
	.iDIG ({addr_out [7:0], data_in [7:0]}),
	.oSEG0 (HEX0), .oSEG1 (HEX1), .oSEG2 (HEX2), .oSEG3 (HEX3)
	);


vga mydisplay (.clk (clk_25mhz), .vga_h_sync (VGA_HS), .vga_v_sync (VGA_VS), .R (VGA_R [3:0]), .G (VGA_G [3:0]), .B (VGA_B [3:0]));


// ---------------------------------------------------------------------------------

wire clk_50mhz, clk_25mhz;
wire reset = ~KEY [0];

pll my_pll (.inclk0 (CLOCK_50), .c0 (clk_25mhz), .c1 (clk_50mhz));


parameter ONESEC = 25'd20000000;
parameter HALFSEC = 25'd100000;

reg [24:0] cntr;

reg [25:0] counter;
always @(posedge clk_25mhz) begin
	counter <= counter + 1'b1;
end


reg [15:0] cntr_1khz;
wire bingo = cntr_1khz == 16'd20000;
always @(posedge clk) begin
	if (reset)
		cntr_1khz <= 0;
	else begin
		if (bingo)
			cntr_1khz <= 0;
		else
			cntr_1khz <= cntr_1khz + 1'b1;
	end
end



assign LEDG [0] = counter [24];

assign LEDG [3] = ~nINDEX;
assign LEDG [4] = ~nRDATA;
assign LEDG [5] = ~nTRK0;
assign LEDG [6] = ~nCHANGE;
assign LEDG [7] = ~nRDY;


//assign LEDR [5:0] = {nINDEX, nCHANGE, nRDY, nRDATA, nTRK0, nWPROT};
//assign LEDR [5:0] = {nINDEX_r, nCHANGE_r, nRDY_r, nRDATA_r, nTRK0_r, nWPROT_r};
assign LEDR [7:0] = ~output_port [7:0];

assign LEDR [8] = rd;
assign LEDR [9] = wr;

endmodule