rendered paste bodydiff --git a/src/r600_exa.c b/src/r600_exa.c
index 0d7e9f9..8af54c0 100644
--- a/src/r600_exa.c
+++ b/src/r600_exa.c
@@ -40,6 +40,8 @@
#include "r600_state.h"
#include "radeon_vbo.h"
+
+
#define RADEON_TRACE_FALL 0
#define RADEON_TRACE_DRAW 0
@@ -191,15 +193,16 @@ R600PrepareSolid(PixmapPtr pPix, int alu, Pixel pm, Pixel fg)
ScrnInfoPtr pScrn = xf86Screens[pPix->drawable.pScreen->myNum];
RADEONInfoPtr info = RADEONPTR(pScrn);
struct radeon_accel_state *accel_state = info->accel_state;
- cb_config_t cb_conf;
- shader_config_t vs_conf, ps_conf;
+/* cb_config_t cb_conf; */
+/* shader_config_t vs_conf, ps_conf; */
int pmask = 0;
uint32_t a, r, g, b;
+ uint32_t cb_color_info;
float ps_alu_consts[4];
- if (!R600CheckBPP(pPix->drawable.bitsPerPixel))
+ if (unlikely(!R600CheckBPP(pPix->drawable.bitsPerPixel)))
RADEON_FALLBACK(("R600CheckDatatype failed\n"));
- if (!R600ValidPM(pm, pPix->drawable.bitsPerPixel))
+ if (unlikely(!R600ValidPM(pm, pPix->drawable.bitsPerPixel)))
RADEON_FALLBACK(("invalid planemask\n"));
#if defined(XF86DRM_MODE)
@@ -209,7 +212,7 @@ R600PrepareSolid(PixmapPtr pPix, int alu, Pixel pm, Pixel fg)
RADEON_GEM_DOMAIN_VRAM, 0);
radeon_add_pixmap(info->cs, pPix, 0, RADEON_GEM_DOMAIN_VRAM);
r = radeon_cs_space_check(info->cs);
- if (r)
+ if (unlikely(r))
RADEON_FALLBACK(("Not enough RAM to hw accel solid operation\n"));
accel_state->dst_mc_addr = 0;
@@ -223,16 +226,16 @@ R600PrepareSolid(PixmapPtr pPix, int alu, Pixel pm, Pixel fg)
accel_state->dst_pitch = exaGetPixmapPitch(pPix) / (pPix->drawable.bitsPerPixel / 8);
/* bad pitch */
- if (accel_state->dst_pitch & 7)
+ if (unlikely(accel_state->dst_pitch & 7))
RADEON_FALLBACK(("Bad pitch 0x%08x\n", accel_state->dst_pitch));
/* bad offset */
- if (accel_state->dst_mc_addr & 0xff)
+ if (unlikely(accel_state->dst_mc_addr & 0xff))
RADEON_FALLBACK(("Bad offset 0x%08x\n", accel_state->dst_mc_addr));
- CLEAR (cb_conf);
- CLEAR (vs_conf);
- CLEAR (ps_conf);
+/* CLEAR (cb_conf); */
+/* CLEAR (vs_conf); */
+/* CLEAR (ps_conf); */
/* return FALSE; */
@@ -244,11 +247,49 @@ R600PrepareSolid(PixmapPtr pPix, int alu, Pixel pm, Pixel fg)
radeon_vbo_check(pScrn, 16);
r600_cp_start(pScrn);
- set_default_state(pScrn, accel_state->ib);
+ if (unlikely(!(accel_state->XInited3D))) set_default_state(pScrn, accel_state->ib);
- set_generic_scissor(pScrn, accel_state->ib, 0, 0, pPix->drawable.width, pPix->drawable.height);
+/* set_generic_scissor(pScrn, accel_state->ib, 0, 0, pPix->drawable.width, pPix->drawable.height);
set_screen_scissor(pScrn, accel_state->ib, 0, 0, pPix->drawable.width, pPix->drawable.height);
+
+set_generic_scissor(ScrnInfoPtr pScrn, drmBufPtr ib, int x1, int y1, int x2, int y2)
+{
+ RADEONInfoPtr info = RADEONPTR(pScrn);
+*/
+ BEGIN_BATCH(18);
+ EREG(accel_state->ib, PA_SC_GENERIC_SCISSOR_TL, WINDOW_OFFSET_DISABLE_bit);
+ EREG(accel_state->ib, PA_SC_GENERIC_SCISSOR_BR, ((pPix->drawable.width << PA_SC_GENERIC_SCISSOR_BR__BR_X_shift) |
+ (pPix->drawable.height << PA_SC_GENERIC_SCISSOR_TL__TL_Y_shift)));
+/* END_BATCH();
+}
+*/
+/*
+set_screen_scissor(ScrnInfoPtr pScrn, drmBufPtr ib, int x1, int y1, int x2, int y2)
+{
+ RADEONInfoPtr info = RADEONPTR(pScrn);
+
+ BEGIN_BATCH(6); */
+ EREG(accel_state->ib, PA_SC_SCREEN_SCISSOR_TL, 0);
+ EREG(accel_state->ib, PA_SC_SCREEN_SCISSOR_BR, ((pPix->drawable.width << PA_SC_SCREEN_SCISSOR_BR__BR_X_shift) |
+ (pPix->drawable.height << PA_SC_SCREEN_SCISSOR_BR__BR_Y_shift)));
+/* END_BATCH();
+ } */
+
+
+/*
set_window_scissor(pScrn, accel_state->ib, 0, 0, pPix->drawable.width, pPix->drawable.height);
+set_window_scissor(ScrnInfoPtr pScrn, drmBufPtr ib, int x1, int y1, int x2, int y2)
+{
+ RADEONInfoPtr info = RADEONPTR(pScrn);
+
+ BEGIN_BATCH(6); */
+ EREG(accel_state->ib, PA_SC_WINDOW_SCISSOR_TL, WINDOW_OFFSET_DISABLE_bit);
+ EREG(accel_state->ib, PA_SC_WINDOW_SCISSOR_BR, ((pPix->drawable.width << PA_SC_WINDOW_SCISSOR_BR__BR_X_shift) |
+ (pPix->drawable.height << PA_SC_WINDOW_SCISSOR_BR__BR_Y_shift)));
+ END_BATCH();
+/* } */
+
+
#if defined(XF86DRM_MODE)
if (info->cs) {
@@ -268,22 +309,57 @@ R600PrepareSolid(PixmapPtr pPix, int alu, Pixel pm, Pixel fg)
/* Shader */
/* flush SQ cache */
- cp_set_surface_sync(pScrn, accel_state->ib, SH_ACTION_ENA_bit,
+/* cp_set_surface_sync(pScrn, accel_state->ib, SH_ACTION_ENA_bit,
accel_state->vs_size, accel_state->vs_mc_addr,
- accel_state->shaders_bo, RADEON_GEM_DOMAIN_VRAM, 0);
+ accel_state->shaders_bo, RADEON_GEM_DOMAIN_VRAM, 0); */
+
+
+ BEGIN_BATCH(50);
+ /* BEGIN_BATCH(7); */
+ /*PACK3(accel_state->ib, IT_SURFACE_SYNC, 4); */
+ E32X5((accel_state->ib), RADEON_CP_PACKET3 | ((IT_SURFACE_SYNC) << 8) | ((3 & 0x3fff) << 16),
+ SH_ACTION_ENA_bit,
+ ((512 + 255) >> 8),
+ (accel_state->vs_mc_addr >> 8),
+ 10); /* poll interval */
+ RELOC_BATCH(accel_state->shaders_bo, RADEON_GEM_DOMAIN_VRAM, 0);
+ /* END_BATCH(); */
- vs_conf.shader_addr = accel_state->vs_mc_addr;
+
+
+/* vs_conf.shader_addr = accel_state->vs_mc_addr;
vs_conf.num_gprs = 2;
vs_conf.stack_size = 0;
vs_conf.bo = accel_state->shaders_bo;
- vs_setup (pScrn, accel_state->ib, &vs_conf, RADEON_GEM_DOMAIN_VRAM);
+ vs_setup (pScrn, accel_state->ib, &vs_conf, RADEON_GEM_DOMAIN_VRAM); */
+
+ /* BEGIN_BATCH(11); */
+ EREG(accel_state->ib, SQ_PGM_START_VS, accel_state->vs_mc_addr >> 8);
+ RELOC_BATCH(accel_state->shaders_bo, RADEON_GEM_DOMAIN_VRAM, 0);
+ EREG(accel_state->ib, SQ_PGM_RESOURCES_VS, 2 << NUM_GPRS_shift);
+ EREG(accel_state->ib, SQ_PGM_CF_OFFSET_VS, 0);
+ /* END_BATCH(); */
+
+
/* flush SQ cache */
- cp_set_surface_sync(pScrn, accel_state->ib, SH_ACTION_ENA_bit,
+/* cp_set_surface_sync(pScrn, accel_state->ib, SH_ACTION_ENA_bit,
accel_state->ps_size, accel_state->ps_mc_addr,
- accel_state->shaders_bo, RADEON_GEM_DOMAIN_VRAM, 0);
+ accel_state->shaders_bo, RADEON_GEM_DOMAIN_VRAM, 0); */
+
+ /* BEGIN_BATCH(7); */
+ /* PACK3(accel_state->ib, IT_SURFACE_SYNC, 4); */
+ E32X5((accel_state->ib), RADEON_CP_PACKET3 | ((IT_SURFACE_SYNC) << 8) | ((3 & 0x3fff) << 16),
+ SH_ACTION_ENA_bit,
+ ((512 + 255) >> 8),
+ (accel_state->ps_mc_addr >> 8),
+ 10); /* poll interval */
+ RELOC_BATCH(accel_state->shaders_bo, RADEON_GEM_DOMAIN_VRAM, 0);
+ /* END_BATCH(); */
- ps_conf.shader_addr = accel_state->ps_mc_addr;
+
+
+/* ps_conf.shader_addr = accel_state->ps_mc_addr;
ps_conf.num_gprs = 1;
ps_conf.stack_size = 0;
ps_conf.uncached_first_inst = 1;
@@ -291,6 +367,18 @@ R600PrepareSolid(PixmapPtr pPix, int alu, Pixel pm, Pixel fg)
ps_conf.export_mode = 2;
ps_conf.bo = accel_state->shaders_bo;
ps_setup (pScrn, accel_state->ib, &ps_conf, RADEON_GEM_DOMAIN_VRAM);
+*/
+
+ /* BEGIN_BATCH(14); */
+ EREG(accel_state->ib, SQ_PGM_START_PS, accel_state->ps_mc_addr >> 8);
+ RELOC_BATCH(accel_state->shaders_bo, RADEON_GEM_DOMAIN_VRAM, 0);
+ EREG(accel_state->ib, SQ_PGM_RESOURCES_PS, ((1 << NUM_GPRS_shift) |
+ (UNCACHED_FIRST_INST_bit)));
+ EREG(accel_state->ib, SQ_PGM_EXPORTS_PS, 2);
+ EREG(accel_state->ib, SQ_PGM_CF_OFFSET_PS, 0);
+ /* END_BATCH(); */
+
+
/* Render setup */
if (pm & 0x000000ff)
@@ -301,30 +389,106 @@ R600PrepareSolid(PixmapPtr pPix, int alu, Pixel pm, Pixel fg)
pmask |= 1; /* R */
if (pm & 0xff000000)
pmask |= 8; /* A */
- BEGIN_BATCH(6);
+/* BEGIN_BATCH(6); */
EREG(accel_state->ib, CB_TARGET_MASK, (pmask << TARGET0_ENABLE_shift));
EREG(accel_state->ib, CB_COLOR_CONTROL, RADEON_ROP[alu]);
- END_BATCH();
-
- cb_conf.id = 0;
- cb_conf.w = accel_state->dst_pitch;
- cb_conf.h = pPix->drawable.height;
- cb_conf.base = accel_state->dst_mc_addr;
- cb_conf.bo = accel_state->dst_bo;
-
- if (pPix->drawable.bitsPerPixel == 8) {
- cb_conf.format = COLOR_8;
- cb_conf.comp_swap = 3; /* A */
+/* END_BATCH(); */
+
+/* cb_conf.id = 0; */
+/* cb_conf.w = accel_state->dst_pitch;
+ cb_conf.h = pPix->drawable.height;
+ cb_conf.base = accel_state->dst_mc_addr;
+ cb_conf.bo = accel_state->dst_bo;
+
+ if (pPix->drawable.bitsPerPixel == 8) {
+ cb_conf.format = COLOR_8;
+ cb_conf.comp_swap = 3; */ /* A */
+/* } else if (pPix->drawable.bitsPerPixel == 16) {
+ cb_conf.format = COLOR_5_6_5;
+ cb_conf.comp_swap = 2; *//* RGB */
+/* } else {
+ cb_conf.format = COLOR_8_8_8_8;
+ cb_conf.comp_swap = 1; */ /* ARGB */
+/* }
+ cb_conf.source_format = 1;
+ cb_conf.blend_clamp = 1;
+ set_render_target(pScrn, accel_state->ib, &cb_conf, RADEON_GEM_DOMAIN_VRAM);
+*/
+
+if (pPix->drawable.bitsPerPixel == 8) {
+ a = (fg >> 0) & 0xff;
+ ps_alu_consts[0] = 0.0; /* R */
+ ps_alu_consts[1] = 0.0; /* G */
+ ps_alu_consts[2] = 0.0; /* B */
+ ps_alu_consts[3] = (float)a / 255; /* A */
+ cb_color_info = (( COLOR_8 << CB_COLOR0_INFO__FORMAT_shift) |
+ (3 << COMP_SWAP_shift) |
+ SOURCE_FORMAT_bit | BLEND_CLAMP_bit);
} else if (pPix->drawable.bitsPerPixel == 16) {
- cb_conf.format = COLOR_5_6_5;
- cb_conf.comp_swap = 2; /* RGB */
+ r = (fg >> 11) & 0x1f;
+ g = (fg >> 5) & 0x3f;
+ b = (fg >> 0) & 0x1f;
+ ps_alu_consts[0] = (float)r / 31; /* R */
+ ps_alu_consts[1] = (float)g / 63; /* G */
+ ps_alu_consts[2] = (float)b / 31; /* B */
+ ps_alu_consts[3] = 1.0; /* A */
+ cb_color_info = ((COLOR_5_6_5 << CB_COLOR0_INFO__FORMAT_shift) |
+ (2 << COMP_SWAP_shift) |
+ SOURCE_FORMAT_bit | BLEND_CLAMP_bit);
} else {
- cb_conf.format = COLOR_8_8_8_8;
- cb_conf.comp_swap = 1; /* ARGB */
+ a = (fg >> 24) & 0xff;
+ r = (fg >> 16) & 0xff;
+ g = (fg >> 8) & 0xff;
+ b = (fg >> 0) & 0xff;
+ ps_alu_consts[0] = (float)r / 255; /* R */
+ ps_alu_consts[1] = (float)g / 255; /* G */
+ ps_alu_consts[2] = (float)b / 255; /* B */
+ ps_alu_consts[3] = (float)a / 255; /* A */
+ cb_color_info = ((COLOR_8_8_8_8 << CB_COLOR0_INFO__FORMAT_shift) |
+ (1 << COMP_SWAP_shift) |
+ SOURCE_FORMAT_bit | BLEND_CLAMP_bit);
}
- cb_conf.source_format = 1;
- cb_conf.blend_clamp = 1;
- set_render_target(pScrn, accel_state->ib, &cb_conf, RADEON_GEM_DOMAIN_VRAM);
+
+
+/* BEGIN_BATCH(3 + 2); */
+ EREG(accel_state->ib, (CB_COLOR0_BASE ), (accel_state->dst_mc_addr >> 8));
+ RELOC_BATCH(accel_state->dst_bo, 0, RADEON_GEM_DOMAIN_VRAM);
+ END_BATCH();
+
+ // rv6xx workaround
+ if ((info->ChipFamily > CHIP_FAMILY_R600) &&
+ (info->ChipFamily < CHIP_FAMILY_RV770)) {
+ BEGIN_BATCH(2);
+/* PACK3(accel_state->ib, IT_SURFACE_BASE_UPDATE, 1); */
+ E32X2(accel_state->ib, RADEON_CP_PACKET3 | ((IT_SURFACE_BASE_UPDATE) << 8),
+ /* E32(accel_state->ib, */ 2 );
+ END_BATCH();
+ }
+ /* Set CMASK & TILE buffer to the offset of color buffer as
+ * we don't use those this shouldn't cause any issue and we
+ * then have a valid cmd stream
+ */
+ BEGIN_BATCH(22);
+/* BEGIN_BATCH(3 + 2); */
+ EREG(accel_state->ib, (CB_COLOR0_TILE ), (0 >> 8)); // CMASK per-tile data base$
+ RELOC_BATCH(accel_state->dst_bo, 0, RADEON_GEM_DOMAIN_VRAM);
+/* END_BATCH();
+ BEGIN_BATCH(3 + 2); */
+ EREG(accel_state->ib, (CB_COLOR0_FRAG ), (0 >> 8)); // FMASK per-tile data base$
+ RELOC_BATCH(accel_state->dst_bo, 0, RADEON_GEM_DOMAIN_VRAM);
+/* END_BATCH();
+ BEGIN_BATCH(12); */
+ // pitch only for ARRAY_LINEAR_GENERAL, other tiling modes require addrlib
+ EREG(accel_state->ib, (CB_COLOR0_SIZE ), ((((accel_state->dst_pitch / 8) - 1) << PITCH_TILE_MAX_shift) |
+ ((((accel_state->dst_pitch * (RADEON_ALIGN(pPix->drawable.height, 8))) / 64) - 1) << SLICE_TILE_MAX_shift)));
+ EREG(accel_state->ib, (CB_COLOR0_VIEW ), ((0 << SLICE_START_shift) |
+ (0 << SLICE_MAX_shift)));
+ EREG(accel_state->ib, (CB_COLOR0_INFO ), cb_color_info);
+ EREG(accel_state->ib, (CB_COLOR0_MASK ), ((0 << CMASK_BLOCK_MAX_shift) |
+ (0 << FMASK_TILE_MAX_shift)));
+ END_BATCH();
+
+
/* Interpolator setup */
/* one unused export from VS (VS_EXPORT_COUNT is zero based, count minus one) */
@@ -346,30 +510,10 @@ R600PrepareSolid(PixmapPtr pPix, int alu, Pixel pm, Pixel fg)
END_BATCH();
/* PS alu constants */
- if (pPix->drawable.bitsPerPixel == 16) {
- r = (fg >> 11) & 0x1f;
- g = (fg >> 5) & 0x3f;
- b = (fg >> 0) & 0x1f;
- ps_alu_consts[0] = (float)r / 31; /* R */
- ps_alu_consts[1] = (float)g / 63; /* G */
- ps_alu_consts[2] = (float)b / 31; /* B */
- ps_alu_consts[3] = 1.0; /* A */
+/* if (pPix->drawable.bitsPerPixel == 16) {
} else if (pPix->drawable.bitsPerPixel == 8) {
- a = (fg >> 0) & 0xff;
- ps_alu_consts[0] = 0.0; /* R */
- ps_alu_consts[1] = 0.0; /* G */
- ps_alu_consts[2] = 0.0; /* B */
- ps_alu_consts[3] = (float)a / 255; /* A */
} else {
- a = (fg >> 24) & 0xff;
- r = (fg >> 16) & 0xff;
- g = (fg >> 8) & 0xff;
- b = (fg >> 0) & 0xff;
- ps_alu_consts[0] = (float)r / 255; /* R */
- ps_alu_consts[1] = (float)g / 255; /* G */
- ps_alu_consts[2] = (float)b / 255; /* B */
- ps_alu_consts[3] = (float)a / 255; /* A */
- }
+ } */
set_alu_consts(pScrn, accel_state->ib, SQ_ALU_CONSTANT_ps,
sizeof(ps_alu_consts) / SQ_ALU_CONSTANT_offset, ps_alu_consts);
@@ -397,14 +541,14 @@ R600Solid(PixmapPtr pPix, int x1, int y1, int x2, int y2)
vb = radeon_vbo_space(pScrn, 8);
- vb[0] = (float)x1;
+ vb[2] = vb[0] = (float)x1;
vb[1] = (float)y1;
- vb[2] = (float)x1;
- vb[3] = (float)y2;
+/* vb[2] = (float)x1; */
+ vb[5] = vb[3] = (float)y2;
vb[4] = (float)x2;
- vb[5] = (float)y2;
+/* vb[5] = (float)y2; */
radeon_vbo_commit(pScrn);
}
@@ -436,16 +580,19 @@ R600DoPrepareCopy(ScrnInfoPtr pScrn,
RADEONInfoPtr info = RADEONPTR(pScrn);
struct radeon_accel_state *accel_state = info->accel_state;
int pmask = 0;
- cb_config_t cb_conf;
- tex_resource_t tex_res;
- tex_sampler_t tex_samp;
- shader_config_t vs_conf, ps_conf;
+ uint32_t cb_color_info;
- CLEAR (cb_conf);
- CLEAR (tex_res);
- CLEAR (tex_samp);
- CLEAR (vs_conf);
- CLEAR (ps_conf);
+ uint32_t sq_tex_resource_word0, sq_tex_resource_word1, sq_tex_resource_word4;
+/* cb_config_t cb_conf; */
+/* tex_resource_t tex_res; */
+/* tex_sampler_t tex_samp; */
+/* shader_config_t vs_conf, ps_conf; */
+
+/* CLEAR (cb_conf); */
+/* CLEAR (tex_res); */
+/* CLEAR (tex_samp); */
+/* CLEAR (vs_conf);
+ CLEAR (ps_conf); */
accel_state->src_size[0] = src_pitch * src_height * (src_bpp/8);
accel_state->src_mc_addr[0] = src_offset;
@@ -466,11 +613,45 @@ R600DoPrepareCopy(ScrnInfoPtr pScrn,
radeon_vbo_check(pScrn, 16);
r600_cp_start(pScrn);
- set_default_state(pScrn, accel_state->ib);
+ if (unlikely(!(accel_state->XInited3D))) set_default_state(pScrn, accel_state->ib);
+
+/* set_generic_scissor(pScrn, accel_state->ib, 0, 0, dst_width, dst_height);
+
+set_generic_scissor(ScrnInfoPtr pScrn, drmBufPtr ib, int x1, int y1, int x2, int y2)
+{
+ RADEONInfoPtr info = RADEONPTR(pScrn);
+*/
+ BEGIN_BATCH(18);
+ EREG(accel_state->ib, PA_SC_GENERIC_SCISSOR_TL, WINDOW_OFFSET_DISABLE_bit);
+ EREG(accel_state->ib, PA_SC_GENERIC_SCISSOR_BR, ((dst_width << PA_SC_GENERIC_SCISSOR_BR__BR_X_shift) |
+ (dst_height << PA_SC_GENERIC_SCISSOR_TL__TL_Y_shift)));
+/* END_BATCH();
+ }
+*/
+/* set_screen_scissor(pScrn, accel_state->ib, 0, 0, dst_width, dst_height);
+set_screen_scissor(ScrnInfoPtr pScrn, drmBufPtr ib, int x1, int y1, int x2, int y2)
+{
+ RADEONInfoPtr info = RADEONPTR(pScrn);
+
+ BEGIN_BATCH(12); */
+ EREG(accel_state->ib, PA_SC_SCREEN_SCISSOR_TL, 0);
+ EREG(accel_state->ib, PA_SC_SCREEN_SCISSOR_BR, ((dst_width << PA_SC_SCREEN_SCISSOR_BR__BR_X_shift) |
+ (dst_height << PA_SC_SCREEN_SCISSOR_BR__BR_Y_shift)));
+/* END_BATCH();
+ } */
+
+
+/* set_window_scissor(pScrn, accel_state->ib, 0, 0, dst_width, dst_height);
+set_window_scissor(ScrnInfoPtr pScrn, drmBufPtr ib, int x1, int y1, int x2, int y2)
+{
+ RADEONInfoPtr info = RADEONPTR(pScrn);
- set_generic_scissor(pScrn, accel_state->ib, 0, 0, dst_width, dst_height);
- set_screen_scissor(pScrn, accel_state->ib, 0, 0, dst_width, dst_height);
- set_window_scissor(pScrn, accel_state->ib, 0, 0, dst_width, dst_height);
+ BEGIN_BATCH(6); */
+ EREG(accel_state->ib, PA_SC_WINDOW_SCISSOR_TL, WINDOW_OFFSET_DISABLE_bit);
+ EREG(accel_state->ib, PA_SC_WINDOW_SCISSOR_BR, ((dst_width << PA_SC_WINDOW_SCISSOR_BR__BR_X_shift) |
+ (dst_height << PA_SC_WINDOW_SCISSOR_BR__BR_Y_shift)));
+ END_BATCH();
+/* } */
#if defined(XF86DRM_MODE)
if (info->cs) {
@@ -490,82 +671,236 @@ R600DoPrepareCopy(ScrnInfoPtr pScrn,
/* Shader */
/* flush SQ cache */
- cp_set_surface_sync(pScrn, accel_state->ib, SH_ACTION_ENA_bit,
+/* cp_set_surface_sync(pScrn, accel_state->ib, SH_ACTION_ENA_bit,
accel_state->vs_size, accel_state->vs_mc_addr,
- accel_state->shaders_bo, RADEON_GEM_DOMAIN_VRAM, 0);
-
- vs_conf.shader_addr = accel_state->vs_mc_addr;
+ accel_state->shaders_bo, RADEON_GEM_DOMAIN_VRAM, 0); */
+ BEGIN_BATCH(39);
+/* BEGIN_BATCH(7); */
+/* PACK3(accel_state->ib, IT_SURFACE_SYNC, 4); */
+ E32X5((accel_state->ib), RADEON_CP_PACKET3 | ((IT_SURFACE_SYNC) << 8) | ((3 & 0x3fff) << 16),
+ SH_ACTION_ENA_bit,
+ ((512 + 255) >> 8),
+ (accel_state->vs_mc_addr >> 8),
+ 10); /* poll interval */
+ RELOC_BATCH(accel_state->shaders_bo, RADEON_GEM_DOMAIN_VRAM, 0);
+/* END_BATCH(); */
+
+
+/* vs_conf.shader_addr = accel_state->vs_mc_addr;
vs_conf.num_gprs = 2;
vs_conf.stack_size = 0;
vs_conf.bo = accel_state->shaders_bo;
- vs_setup (pScrn, accel_state->ib, &vs_conf, RADEON_GEM_DOMAIN_VRAM);
+ vs_setup (pScrn, accel_state->ib, &vs_conf, RADEON_GEM_DOMAIN_VRAM); */
+
+
+/* BEGIN_BATCH(11); */
+ EREG(accel_state->ib, SQ_PGM_START_VS, accel_state->vs_mc_addr >> 8);
+ RELOC_BATCH(accel_state->shaders_bo, RADEON_GEM_DOMAIN_VRAM, 0);
+ EREG(accel_state->ib, SQ_PGM_RESOURCES_VS, 2 << NUM_GPRS_shift);
+ EREG(accel_state->ib, SQ_PGM_CF_OFFSET_VS, 0);
+/* END_BATCH(); */
+
/* flush SQ cache */
- cp_set_surface_sync(pScrn, accel_state->ib, SH_ACTION_ENA_bit,
+/* cp_set_surface_sync(pScrn, accel_state->ib, SH_ACTION_ENA_bit,
accel_state->ps_size, accel_state->ps_mc_addr,
- accel_state->shaders_bo, RADEON_GEM_DOMAIN_VRAM, 0);
+ accel_state->shaders_bo, RADEON_GEM_DOMAIN_VRAM, 0); */
- ps_conf.shader_addr = accel_state->ps_mc_addr;
+
+/* BEGIN_BATCH(7); */
+/* PACK3(accel_state->ib, IT_SURFACE_SYNC, 4); */
+ E32X5((accel_state->ib), RADEON_CP_PACKET3 | ((IT_SURFACE_SYNC) << 8) | ((3 & 0x3fff) << 16),
+ SH_ACTION_ENA_bit,
+ ((512 + 255) >> 8),
+ (accel_state->ps_mc_addr >> 8),
+ 10); /* poll interval */
+ RELOC_BATCH(accel_state->shaders_bo, RADEON_GEM_DOMAIN_VRAM, 0);
+/* END_BATCH(); */
+
+
+
+/* ps_conf.shader_addr = accel_state->ps_mc_addr;
ps_conf.num_gprs = 1;
ps_conf.stack_size = 0;
ps_conf.uncached_first_inst = 1;
ps_conf.clamp_consts = 0;
ps_conf.export_mode = 2;
ps_conf.bo = accel_state->shaders_bo;
- ps_setup (pScrn, accel_state->ib, &ps_conf, RADEON_GEM_DOMAIN_VRAM);
+ ps_setup (pScrn, accel_state->ib, &ps_conf, RADEON_GEM_DOMAIN_VRAM);*/
+
+/* BEGIN_BATCH(14); */
+ EREG(accel_state->ib, SQ_PGM_START_PS, accel_state->ps_mc_addr >> 8);
+ RELOC_BATCH(accel_state->shaders_bo, RADEON_GEM_DOMAIN_VRAM, 0);
+ EREG(accel_state->ib, SQ_PGM_RESOURCES_PS, ((1 << NUM_GPRS_shift) |
+ (UNCACHED_FIRST_INST_bit)));
+ EREG(accel_state->ib, SQ_PGM_EXPORTS_PS, 2);
+ EREG(accel_state->ib, SQ_PGM_CF_OFFSET_PS, 0);
+ END_BATCH();
+
/* flush texture cache */
- cp_set_surface_sync(pScrn, accel_state->ib, TC_ACTION_ENA_bit,
+/* cp_set_surface_sync(pScrn, accel_state->ib, TC_ACTION_ENA_bit,
accel_state->src_size[0], accel_state->src_mc_addr[0],
- accel_state->src_bo[0], RADEON_GEM_DOMAIN_VRAM | RADEON_GEM_DOMAIN_GTT, 0);
+ accel_state->src_bo[0], RADEON_GEM_DOMAIN_VRAM | RADEON_GEM_DOMAIN_GTT, 0); */
+
+ BEGIN_BATCH(7);
+/* PACK3(accel_state->ib, IT_SURFACE_SYNC, 4); */
+ E32X5((accel_state->ib), RADEON_CP_PACKET3 | ((IT_SURFACE_SYNC) << 8) | ((3 & 0x3fff) << 16),
+ TC_ACTION_ENA_bit,
+ (accel_state->src_size[0] == 0xFFFFFFFF) ? 0xFFFFFFFF : ((accel_state->src_size[0] + 255) >> 8),
+ (accel_state->src_mc_addr[0] >> 8),
+ 10); /* poll interval */
+ RELOC_BATCH(accel_state->src_bo[0], RADEON_GEM_DOMAIN_VRAM | RADEON_GEM_DOMAIN_GTT, 0);
+ END_BATCH();
+
+
/* Texture */
- tex_res.id = 0;
+/* tex_res.id = 0;
tex_res.w = src_width;
tex_res.h = src_height;
tex_res.pitch = accel_state->src_pitch[0];
tex_res.depth = 0;
tex_res.dim = SQ_TEX_DIM_2D;
+ tex_res.tile_mode = 0;
+ tex_res.tile_type = 0;
tex_res.base = accel_state->src_mc_addr[0];
tex_res.mip_base = accel_state->src_mc_addr[0];
+ tex_res.format_comp_x = 0;
+ tex_res.format_comp_y = 0;
+ tex_res.format_comp_z = 0;
+ tex_res.format_comp_w = 0;
+ tex_res.num_format_all = 0;
+ tex_res.srf_mode_all = 0;
+ tex_res.force_degamma = 0;
+ tex_res.endian = 0;
+ tex_res.request_size = 1;
+ if (src_bpp == 8) {
+ tex_res.format = FMT_8;
+ tex_res.dst_sel_x = SQ_SEL_1; */ /* R */
+/* tex_res.dst_sel_y = SQ_SEL_1; */ /* G */
+/* tex_res.dst_sel_z = SQ_SEL_1; */ /* B */
+/* tex_res.dst_sel_w = SQ_SEL_X; */ /* A */
+/* } else if (src_bpp == 16) {
+ tex_res.format = FMT_5_6_5;
+ tex_res.dst_sel_x = SQ_SEL_Z; */ /* R */
+/* tex_res.dst_sel_y = SQ_SEL_Y; */ /* G */
+/* tex_res.dst_sel_z = SQ_SEL_X; */ /* B */
+/* tex_res.dst_sel_w = SQ_SEL_1; */ /* A */
+/* } else {
+ tex_res.format = FMT_8_8_8_8;
+ tex_res.dst_sel_x = SQ_SEL_Z; */ /* R */
+/* tex_res.dst_sel_y = SQ_SEL_Y; */ /* G */
+/* tex_res.dst_sel_z = SQ_SEL_X; */ /* B */
+/* tex_res.dst_sel_w = SQ_SEL_W; */ /* A */
+/* }
+
+ tex_res.base_level = 0;
+ tex_res.last_level = 0;
+ tex_res.base_array = 0;
+ tex_res.last_array = 0;
+ tex_res.mpeg_clamp = 0;
+ tex_res.perf_modulation = 0;
+ tex_res.interlaced = 0;
tex_res.bo = accel_state->src_bo[0];
tex_res.mip_bo = accel_state->src_bo[0];
+
+ set_tex_resource (pScrn, accel_state->ib, &tex_res, RADEON_GEM_DOMAIN_VRAM | RADEON_GEM_DOMAIN_GTT);
+*/
+
+ sq_tex_resource_word0 =( SQ_TEX_DIM_2D << DIM_shift);
+
+ if (src_width)
+ sq_tex_resource_word0 |= (((((accel_state->src_pitch[0] + 7) >> 3) - 1) << PITCH_shift) |
+ ((src_width - 1) << TEX_WIDTH_shift));
+
if (src_bpp == 8) {
- tex_res.format = FMT_8;
- tex_res.dst_sel_x = SQ_SEL_1; /* R */
- tex_res.dst_sel_y = SQ_SEL_1; /* G */
- tex_res.dst_sel_z = SQ_SEL_1; /* B */
- tex_res.dst_sel_w = SQ_SEL_X; /* A */
+ sq_tex_resource_word1 = ( FMT_8 << SQ_TEX_RESOURCE_WORD1_0__DATA_FORMAT_shift);
+ sq_tex_resource_word4 = ( (1 << REQUEST_SIZE_shift) |
+ (SQ_SEL_1 << SQ_TEX_RESOURCE_WORD4_0__DST_SEL_X_shift) |
+ (SQ_SEL_1 << SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Y_shift) |
+ (SQ_SEL_1 << SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Z_shift) |
+ (SQ_SEL_X << SQ_TEX_RESOURCE_WORD4_0__DST_SEL_W_shift));
} else if (src_bpp == 16) {
- tex_res.format = FMT_5_6_5;
- tex_res.dst_sel_x = SQ_SEL_Z; /* R */
- tex_res.dst_sel_y = SQ_SEL_Y; /* G */
- tex_res.dst_sel_z = SQ_SEL_X; /* B */
- tex_res.dst_sel_w = SQ_SEL_1; /* A */
+ sq_tex_resource_word1 = (FMT_5_6_5 << SQ_TEX_RESOURCE_WORD1_0__DATA_FORMAT_shift);
+ sq_tex_resource_word4 = ( (1 << REQUEST_SIZE_shift) |
+ (SQ_SEL_Z << SQ_TEX_RESOURCE_WORD4_0__DST_SEL_X_shift) |
+ (SQ_SEL_Y << SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Y_shift) |
+ (SQ_SEL_X << SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Z_shift) |
+ (SQ_SEL_1 << SQ_TEX_RESOURCE_WORD4_0__DST_SEL_W_shift));
} else {
- tex_res.format = FMT_8_8_8_8;
- tex_res.dst_sel_x = SQ_SEL_Z; /* R */
- tex_res.dst_sel_y = SQ_SEL_Y; /* G */
- tex_res.dst_sel_z = SQ_SEL_X; /* B */
- tex_res.dst_sel_w = SQ_SEL_W; /* A */
+ sq_tex_resource_word1 = (FMT_8_8_8_8 << SQ_TEX_RESOURCE_WORD1_0__DATA_FORMAT_shift);
+ sq_tex_resource_word4 = ( (1 << REQUEST_SIZE_shift) |
+ (SQ_SEL_Z << SQ_TEX_RESOURCE_WORD4_0__DST_SEL_X_shift) |
+ (SQ_SEL_Y << SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Y_shift) |
+ (SQ_SEL_X << SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Z_shift) |
+ (SQ_SEL_W << SQ_TEX_RESOURCE_WORD4_0__DST_SEL_W_shift));
+
}
- tex_res.request_size = 1;
- tex_res.base_level = 0;
- tex_res.last_level = 0;
- tex_res.perf_modulation = 0;
- set_tex_resource (pScrn, accel_state->ib, &tex_res, RADEON_GEM_DOMAIN_VRAM | RADEON_GEM_DOMAIN_GTT);
+ if (src_height)
+ sq_tex_resource_word1 |= ((src_height - 1) << TEX_HEIGHT_shift);
+
+
+
+
+ BEGIN_BATCH(18);
+/* BEGIN_BATCH(9 + 4); */
+ PACK0(accel_state->ib, SQ_TEX_RESOURCE , 7);
+ E32X7(accel_state->ib, sq_tex_resource_word0,
+ /* E32(ib, */ sq_tex_resource_word1,
+ /* E32(ib, */ ((accel_state->src_mc_addr[0]) >> 8),
+ /* E32(ib, */ ((accel_state->src_mc_addr[0]) >> 8),
+ /* E32(ib, */ sq_tex_resource_word4,
+ /* E32(ib, */ 0,
+ /* E32(ib, */ (SQ_TEX_VTX_VALID_TEXTURE << SQ_TEX_RESOURCE_WORD6_0__TYPE_shift));
+ RELOC_BATCH(accel_state->src_bo[0], RADEON_GEM_DOMAIN_VRAM | RADEON_GEM_DOMAIN_GTT, 0);
+ RELOC_BATCH(accel_state->src_bo[0], RADEON_GEM_DOMAIN_VRAM | RADEON_GEM_DOMAIN_GTT, 0);
+/* END_BATCH(); */
+
+/*
tex_samp.id = 0;
tex_samp.clamp_x = SQ_TEX_CLAMP_LAST_TEXEL;
tex_samp.clamp_y = SQ_TEX_CLAMP_LAST_TEXEL;
tex_samp.clamp_z = SQ_TEX_WRAP;
+ tex_samp.border_color = 0;
tex_samp.xy_mag_filter = SQ_TEX_XY_FILTER_POINT;
tex_samp.xy_min_filter = SQ_TEX_XY_FILTER_POINT;
tex_samp.z_filter = SQ_TEX_Z_FILTER_NONE;
- tex_samp.mip_filter = 0; /* no mipmap */
- set_tex_sampler (pScrn, accel_state->ib, &tex_samp);
+ tex_samp.mip_filter = 0; */ /* no mipmap */
+/* tex_samp.high_precision_filter = FALSE;
+ tex_samp.perf_mip = 0;
+ tex_samp.perf_z = 0;
+ tex_samp.min_lod = 0;
+ tex_samp.max_lod = 0;
+ tex_samp.lod_bias = 0;
+ tex_samp.lod_bias2 = 0;
+ tex_samp.lod_uses_minor_axis = FALSE;
+ tex_samp.point_sampling_clamp = FALSE;
+ tex_samp.tex_array_override = FALSE;
+ tex_samp.mc_coord_truncate = FALSE;
+ tex_samp.force_degamma = FALSE;
+ tex_samp.fetch_4 = FALSE;
+ tex_samp.sample_is_pcf = FALSE;
+ tex_samp.type = FALSE;
+ tex_samp.depth_compare = 0;
+ tex_samp.chroma_key = 0;
+ set_tex_sampler (pScrn, accel_state->ib, &tex_samp);
+
+ */
+/* BEGIN_BATCH(5); */
+ PACK0(accel_state->ib, SQ_TEX_SAMPLER_WORD , 3);
+ E32X3(accel_state->ib, ((SQ_TEX_CLAMP_LAST_TEXEL << SQ_TEX_SAMPLER_WORD0_0__CLAMP_X_shift) |
+ (SQ_TEX_CLAMP_LAST_TEXEL << CLAMP_Y_shift) |
+ (SQ_TEX_WRAP << CLAMP_Z_shift) |
+ (SQ_TEX_XY_FILTER_POINT << XY_MAG_FILTER_shift) |
+ (SQ_TEX_XY_FILTER_POINT << XY_MIN_FILTER_shift) |
+ (SQ_TEX_Z_FILTER_NONE << Z_FILTER_shift)),
+ /* E32(ib, */ 0,
+ /* E32(ib, */ 0);
+ END_BATCH();
/* Render setup */
if (planemask & 0x000000ff)
@@ -576,29 +911,88 @@ R600DoPrepareCopy(ScrnInfoPtr pScrn,
pmask |= 1; /* R */
if (planemask & 0xff000000)
pmask |= 8; /* A */
- BEGIN_BATCH(6);
+ BEGIN_BATCH(11);
+/* BEGIN_BATCH(6); */
EREG(accel_state->ib, CB_TARGET_MASK, (pmask << TARGET0_ENABLE_shift));
EREG(accel_state->ib, CB_COLOR_CONTROL, RADEON_ROP[rop]);
- END_BATCH();
+/* END_BATCH(); */
- cb_conf.id = 0;
+/* cb_conf.id = 0;
cb_conf.w = accel_state->dst_pitch;
cb_conf.h = dst_height;
cb_conf.base = accel_state->dst_mc_addr;
cb_conf.bo = accel_state->dst_bo;
if (dst_bpp == 8) {
- cb_conf.format = COLOR_8;
- cb_conf.comp_swap = 3; /* A */
- } else if (dst_bpp == 16) {
- cb_conf.format = COLOR_5_6_5;
- cb_conf.comp_swap = 2; /* RGB */
- } else {
- cb_conf.format = COLOR_8_8_8_8;
- cb_conf.comp_swap = 1; /* ARGB */
- }
+ cb_conf.format = COLOR_8;
+ cb_conf.comp_swap = 3;*/ /* A */
+/* } else if (dst_bpp == 16) {
+ cb_conf.format = COLOR_5_6_5;
+ cb_conf.comp_swap = 2;*/ /* RGB */
+/* } else {
+ cb_conf.format = COLOR_8_8_8_8;
+ cb_conf.comp_swap = 1;*/ /* ARGB */
+/* }
cb_conf.source_format = 1;
cb_conf.blend_clamp = 1;
set_render_target(pScrn, accel_state->ib, &cb_conf, RADEON_GEM_DOMAIN_VRAM | RADEON_GEM_DOMAIN_GTT);
+*/
+
+
+if (dst_bpp == 8) {
+ cb_color_info = (( COLOR_8 << CB_COLOR0_INFO__FORMAT_shift) |
+ (3 << COMP_SWAP_shift) |
+ SOURCE_FORMAT_bit | BLEND_CLAMP_bit);
+ } else if (dst_bpp == 16) {
+ cb_color_info = ((COLOR_5_6_5 << CB_COLOR0_INFO__FORMAT_shift) |
+ (2 << COMP_SWAP_shift) |
+ SOURCE_FORMAT_bit | BLEND_CLAMP_bit);
+ } else {
+ cb_color_info = ((COLOR_8_8_8_8 << CB_COLOR0_INFO__FORMAT_shift) |
+ (1 << COMP_SWAP_shift) |
+ SOURCE_FORMAT_bit | BLEND_CLAMP_bit);
+ }
+
+/* BEGIN_BATCH(3 + 2); */
+ EREG(accel_state->ib, (CB_COLOR0_BASE ), (accel_state->dst_mc_addr >> 8));
+ RELOC_BATCH(accel_state->dst_bo, 0, RADEON_GEM_DOMAIN_VRAM | RADEON_GEM_DOMAIN_GTT);
+ END_BATCH();
+
+ // rv6xx workaround
+ if ((info->ChipFamily > CHIP_FAMILY_R600) &&
+ (info->ChipFamily < CHIP_FAMILY_RV770)) {
+ BEGIN_BATCH(2);
+/* PACK3(accel_state->ib, IT_SURFACE_BASE_UPDATE, 1); */
+ E32X2(accel_state->ib, RADEON_CP_PACKET3 | ((IT_SURFACE_BASE_UPDATE) << 8),
+ /* E32(accel_state->ib, */ 2 );
+ END_BATCH();
+ }
+ /* Set CMASK & TILE buffer to the offset of color buffer as
+ * we don't use those this shouldn't cause any issue and we
+ * then have a valid cmd stream
+ */
+ BEGIN_BATCH(22);
+/* BEGIN_BATCH(3 + 2); */
+ EREG(accel_state->ib, (CB_COLOR0_TILE ), (0 >> 8)); // CMASK per-tile data base$
+ RELOC_BATCH(accel_state->dst_bo, 0, RADEON_GEM_DOMAIN_VRAM | RADEON_GEM_DOMAIN_GTT);
+/* END_BATCH();
+ BEGIN_BATCH(3 + 2); */
+ EREG(accel_state->ib, (CB_COLOR0_FRAG ), (0 >> 8)); // FMASK per-tile data base$
+ RELOC_BATCH(accel_state->dst_bo, 0, RADEON_GEM_DOMAIN_VRAM | RADEON_GEM_DOMAIN_GTT);
+/* END_BATCH();
+ BEGIN_BATCH(12); */
+ // pitch only for ARRAY_LINEAR_GENERAL, other tiling modes require addrlib
+ EREG(accel_state->ib, (CB_COLOR0_SIZE ), ((((accel_state->dst_pitch / 8) - 1) << PITCH_TILE_MAX_shift) |
+ ((((accel_state->dst_pitch * (RADEON_ALIGN(dst_height, 8))) / 64) - 1) << SLICE_TILE_MAX_shift)));
+ EREG(accel_state->ib, (CB_COLOR0_VIEW ), ((0 << SLICE_START_shift) |
+ (0 << SLICE_MAX_shift)));
+ EREG(accel_state->ib, (CB_COLOR0_INFO ), cb_color_info);
+ EREG(accel_state->ib, (CB_COLOR0_MASK ), ((0 << CMASK_BLOCK_MAX_shift) |
+ (0 << FMASK_TILE_MAX_shift)));
+ END_BATCH();
+
+
+
+
/* Interpolator setup */
/* export tex coord from VS */
@@ -652,20 +1046,20 @@ R600AppendCopyVertex(ScrnInfoPtr pScrn,
vb = radeon_vbo_space(pScrn, 16);
- vb[0] = (float)dstX;
+ vb[4] = vb[0] = (float)dstX;
vb[1] = (float)dstY;
- vb[2] = (float)srcX;
+ vb[6] = vb[2] = (float)srcX;
vb[3] = (float)srcY;
- vb[4] = (float)dstX;
- vb[5] = (float)(dstY + h);
- vb[6] = (float)srcX;
- vb[7] = (float)(srcY + h);
+/* vb[4] = (float)dstX; */
+ vb[9] = vb[5] = (float)(dstY + h);
+/* vb[6] = (float)srcX; */
+ vb[11] = vb[7] = (float)(srcY + h);
vb[8] = (float)(dstX + w);
- vb[9] = (float)(dstY + h);
+/* vb[9] = (float)(dstY + h); */
vb[10] = (float)(srcX + w);
- vb[11] = (float)(srcY + h);
+/* vb[11] = (float)(srcY + h); */
radeon_vbo_commit(pScrn);
}
@@ -680,11 +1074,11 @@ R600PrepareCopy(PixmapPtr pSrc, PixmapPtr pDst,
RADEONInfoPtr info = RADEONPTR(pScrn);
struct radeon_accel_state *accel_state = info->accel_state;
- if (!R600CheckBPP(pSrc->drawable.bitsPerPixel))
+ if (unlikely(!R600CheckBPP(pSrc->drawable.bitsPerPixel)))
RADEON_FALLBACK(("R600CheckDatatype src failed\n"));
- if (!R600CheckBPP(pDst->drawable.bitsPerPixel))
+ if (unlikely(!R600CheckBPP(pDst->drawable.bitsPerPixel)))
RADEON_FALLBACK(("R600CheckDatatype dst failed\n"));
- if (!R600ValidPM(planemask, pDst->drawable.bitsPerPixel))
+ if (unlikely(!R600ValidPM(planemask, pDst->drawable.bitsPerPixel)))
RADEON_FALLBACK(("Invalid planemask\n"));
accel_state->dst_pitch = exaGetPixmapPitch(pDst) / (pDst->drawable.bitsPerPixel / 8);
@@ -716,16 +1110,16 @@ R600PrepareCopy(PixmapPtr pSrc, PixmapPtr pDst,
accel_state->dst_bpp = pDst->drawable.bitsPerPixel;
/* bad pitch */
- if (accel_state->src_pitch[0] & 7)
+ if (unlikely(accel_state->src_pitch[0] & 7))
RADEON_FALLBACK(("Bad src pitch 0x%08x\n", accel_state->src_pitch[0]));
- if (accel_state->dst_pitch & 7)
+ if (unlikely(accel_state->dst_pitch & 7))
RADEON_FALLBACK(("Bad dst pitch 0x%08x\n", accel_state->dst_pitch));
/* bad offset */
- if (accel_state->src_mc_addr[0] & 0xff)
+ if (unlikely(accel_state->src_mc_addr[0] & 0xff))
RADEON_FALLBACK(("Bad src offset 0x%08x\n", accel_state->src_mc_addr[0]));
- if (accel_state->dst_mc_addr & 0xff)
+ if (unlikely(accel_state->dst_mc_addr & 0xff))
RADEON_FALLBACK(("Bad dst offset 0x%08x\n", accel_state->dst_mc_addr));
#if defined(XF86DRM_MODE)
@@ -738,7 +1132,7 @@ R600PrepareCopy(PixmapPtr pSrc, PixmapPtr pDst,
radeon_add_pixmap(info->cs, pSrc, RADEON_GEM_DOMAIN_GTT | RADEON_GEM_DOMAIN_VRAM, 0);
radeon_add_pixmap(info->cs, pDst, 0, RADEON_GEM_DOMAIN_VRAM);
ret = radeon_cs_space_check(info->cs);
- if (ret)
+ if (unlikely(ret))
RADEON_FALLBACK(("Not enough RAM to hw accel copy operation\n"));
}
#endif
@@ -767,12 +1161,12 @@ R600PrepareCopy(PixmapPtr pSrc, PixmapPtr pDst,
accel_state->copy_area_bo = radeon_bo_open(info->bufmgr, 0, size, 0,
RADEON_GEM_DOMAIN_VRAM,
0);
- if (accel_state->copy_area_bo == NULL) {
+ if (unlikely(accel_state->copy_area_bo == NULL)) {
return FALSE;
}
radeon_cs_space_add_persistent_bo(info->cs, accel_state->copy_area_bo,
0, RADEON_GEM_DOMAIN_VRAM);
- if (radeon_cs_space_check(info->cs)) {
+ if (unlikely(radeon_cs_space_check(info->cs))) {
radeon_bo_unref(accel_state->copy_area_bo);
accel_state->copy_area_bo = NULL;
return FALSE;
@@ -983,7 +1377,7 @@ R600Copy(PixmapPtr pDst,
struct radeon_accel_state *accel_state = info->accel_state;
struct radeon_bo *bo = NULL;
- if (accel_state->same_surface && (srcX == dstX) && (srcY == dstY))
+ if (unlikely(accel_state->same_surface && (srcX == dstX) && (srcY == dstY)))
return;
if (accel_state->vsync)
@@ -1206,19 +1600,19 @@ static Bool R600CheckCompositeTexture(PicturePtr pPict,
max_tex_w = 8192;
max_tex_h = 8192;
- if ((w > max_tex_w) || (h > max_tex_h))
+ if (unlikely((w > max_tex_w) || (h > max_tex_h)))
RADEON_FALLBACK(("Picture w/h too large (%dx%d)\n", w, h));
for (i = 0; i < sizeof(R600TexFormats) / sizeof(R600TexFormats[0]); i++) {
if (R600TexFormats[i].fmt == pPict->format)
break;
}
- if (i == sizeof(R600TexFormats) / sizeof(R600TexFormats[0]))
+ if (unlikely(i == sizeof(R600TexFormats) / sizeof(R600TexFormats[0])))
RADEON_FALLBACK(("Unsupported picture format 0x%x\n",
(int)pPict->format));
- if (pPict->filter != PictFilterNearest &&
- pPict->filter != PictFilterBilinear)
+ if (unlikely(pPict->filter != PictFilterNearest &&
+ pPict->filter != PictFilterBilinear))
RADEON_FALLBACK(("Unsupported filter 0x%x\n", pPict->filter));
/* for REPEAT_NONE, Render semantics are that sampling outside the source
@@ -1253,8 +1647,8 @@ static Bool R600TextureSetup(PicturePtr pPict, PixmapPtr pPix,
int pix_r, pix_g, pix_b, pix_a;
float vs_alu_consts[8];
- CLEAR (tex_res);
- CLEAR (tex_samp);
+/* CLEAR (tex_res); */
+/* CLEAR (tex_samp); */
#if defined(XF86DRM_MODE)
if (info->cs) {
@@ -1265,10 +1659,10 @@ static Bool R600TextureSetup(PicturePtr pPict, PixmapPtr pPix,
accel_state->src_pitch[unit] = exaGetPixmapPitch(pPix) / (pPix->drawable.bitsPerPixel / 8);
accel_state->src_size[unit] = exaGetPixmapPitch(pPix) * pPix->drawable.height;
- if (accel_state->src_pitch[unit] & 7)
+ if (unlikely(accel_state->src_pitch[unit] & 7))
RADEON_FALLBACK(("Bad pitch %d 0x%x\n", (int)accel_state->src_pitch[unit], unit));
- if (accel_state->src_mc_addr[unit] & 0xff)
+ if (unlikely(accel_state->src_mc_addr[unit] & 0xff))
RADEON_FALLBACK(("Bad offset %d 0x%x\n", (int)accel_state->src_mc_addr[unit], unit));
for (i = 0; i < sizeof(R600TexFormats) / sizeof(R600TexFormats[0]); i++) {
@@ -1279,9 +1673,22 @@ static Bool R600TextureSetup(PicturePtr pPict, PixmapPtr pPix,
/* ErrorF("Tex %d setup %dx%d\n", unit, w, h); */
/* flush texture cache */
- cp_set_surface_sync(pScrn, accel_state->ib, TC_ACTION_ENA_bit,
+/* cp_set_surface_sync(pScrn, accel_state->ib, TC_ACTION_ENA_bit,
accel_state->src_size[unit], accel_state->src_mc_addr[unit],
accel_state->src_bo[unit], RADEON_GEM_DOMAIN_VRAM | RADEON_GEM_DOMAIN_GTT, 0);
+*/
+
+ BEGIN_BATCH(7);
+ /* PACK3(accel_state->ib, IT_SURFACE_SYNC, 4); */
+ E32X5((accel_state->ib), RADEON_CP_PACKET3 | ((IT_SURFACE_SYNC) << 8) | ((3 & 0x3fff) << 16),
+ /* E32(accel_state->ib, */ TC_ACTION_ENA_bit,
+ /* E32(accel_state->ib, */ (accel_state->src_size[unit] == 0xFFFFFFFF) ? 0xFFFFFFFF : ((accel_state->src_size[unit] + 255) >> 8),
+ /* E32(accel_state->ib, */ (accel_state->src_mc_addr[unit] >> 8),
+ /* E32(accel_state->ib, */ 10); /* poll interval */
+ RELOC_BATCH(accel_state->src_bo[unit], RADEON_GEM_DOMAIN_VRAM | RADEON_GEM_DOMAIN_GTT, 0);
+ END_BATCH();
+
+
/* Texture */
tex_res.id = unit;
@@ -1290,11 +1697,19 @@ static Bool R600TextureSetup(PicturePtr pPict, PixmapPtr pPix,
tex_res.pitch = accel_state->src_pitch[unit];
tex_res.depth = 0;
tex_res.dim = SQ_TEX_DIM_2D;
+ tex_res.tile_mode = 0;
+ tex_res.tile_type = 0;
+ tex_res.format = R600TexFormats[i].card_fmt;
tex_res.base = accel_state->src_mc_addr[unit];
tex_res.mip_base = accel_state->src_mc_addr[unit];
- tex_res.format = R600TexFormats[i].card_fmt;
- tex_res.bo = accel_state->src_bo[unit];
- tex_res.mip_bo = accel_state->src_bo[unit];
+ tex_res.format_comp_x = 0;
+ tex_res.format_comp_y = 0;
+ tex_res.format_comp_z = 0;
+ tex_res.format_comp_w = 0;
+ tex_res.num_format_all = 0;
+ tex_res.srf_mode_all = 0;
+ tex_res.force_degamma = 0;
+ tex_res.endian = 0;
tex_res.request_size = 1;
/* component swizzles */
@@ -1406,6 +1821,7 @@ static Bool R600TextureSetup(PicturePtr pPict, PixmapPtr pPix,
}
}
+
tex_res.dst_sel_x = pix_r; /* R */
tex_res.dst_sel_y = pix_g; /* G */
tex_res.dst_sel_z = pix_b; /* B */
@@ -1413,11 +1829,16 @@ static Bool R600TextureSetup(PicturePtr pPict, PixmapPtr pPix,
tex_res.base_level = 0;
tex_res.last_level = 0;
+ tex_res.base_array = 0;
+ tex_res.last_array = 0;
+ tex_res.mpeg_clamp = 0;
tex_res.perf_modulation = 0;
+ tex_res.interlaced = 0;
+ tex_res.bo = accel_state->src_bo[unit];
+ tex_res.mip_bo = accel_state->src_bo[unit];
set_tex_resource (pScrn, accel_state->ib, &tex_res, RADEON_GEM_DOMAIN_VRAM | RADEON_GEM_DOMAIN_GTT);
tex_samp.id = unit;
- tex_samp.border_color = SQ_TEX_BORDER_COLOR_TRANS_BLACK;
switch (repeatType) {
case RepeatNormal:
@@ -1439,6 +1860,8 @@ static Bool R600TextureSetup(PicturePtr pPict, PixmapPtr pPix,
default:
RADEON_FALLBACK(("Bad repeat 0x%x\n", repeatType));
}
+ tex_samp.clamp_z = SQ_TEX_WRAP;
+ tex_samp.border_color = SQ_TEX_BORDER_COLOR_TRANS_BLACK;
switch (pPict->filter) {
case PictFilterNearest:
@@ -1453,9 +1876,26 @@ static Bool R600TextureSetup(PicturePtr pPict, PixmapPtr pPix,
RADEON_FALLBACK(("Bad filter 0x%x\n", pPict->filter));
}
- tex_samp.clamp_z = SQ_TEX_WRAP;
tex_samp.z_filter = SQ_TEX_Z_FILTER_NONE;
- tex_samp.mip_filter = 0; /* no mipmap */
+ tex_samp.mip_filter = 0; /* no mipmap */
+ tex_samp.high_precision_filter = FALSE;
+ tex_samp.perf_mip = 0;
+ tex_samp.perf_z = 0;
+ tex_samp.min_lod = 0;
+ tex_samp.max_lod = 0;
+ tex_samp.lod_bias = 0;
+ tex_samp.lod_bias2 = 0;
+ tex_samp.lod_uses_minor_axis = FALSE;
+ tex_samp.point_sampling_clamp = FALSE;
+ tex_samp.tex_array_override = FALSE;
+ tex_samp.mc_coord_truncate = FALSE;
+ tex_samp.force_degamma = FALSE;
+ tex_samp.fetch_4 = FALSE;
+ tex_samp.sample_is_pcf = FALSE;
+ tex_samp.type = FALSE;
+ tex_samp.depth_compare = 0;
+ tex_samp.chroma_key = 0;
+
set_tex_sampler (pScrn, accel_state->ib, &tex_samp);
if (pPict->transform != 0) {
@@ -1500,10 +1940,10 @@ static Bool R600CheckComposite(int op, PicturePtr pSrcPicture, PicturePtr pMaskP
int max_tex_w, max_tex_h, max_dst_w, max_dst_h;
/* Check for unsupported compositing operations. */
- if (op >= (int) (sizeof(R600BlendOp) / sizeof(R600BlendOp[0])))
+ if (unlikely(op >= (int) (sizeof(R600BlendOp) / sizeof(R600BlendOp[0]))))
RADEON_FALLBACK(("Unsupported Composite op 0x%x\n", op));
- if (!pSrcPicture->pDrawable)
+ if (unlikely(!pSrcPicture->pDrawable))
RADEON_FALLBACK(("Solid or gradient pictures not supported yet\n"));
pSrcPixmap = RADEONGetDrawablePixmap(pSrcPicture->pDrawable);
@@ -1513,8 +1953,8 @@ static Bool R600CheckComposite(int op, PicturePtr pSrcPicture, PicturePtr pMaskP
max_dst_w = 8192;
max_dst_h = 8192;
- if (pSrcPixmap->drawable.width >= max_tex_w ||
- pSrcPixmap->drawable.height >= max_tex_h) {
+ if (unlikely(pSrcPixmap->drawable.width >= max_tex_w ||
+ pSrcPixmap->drawable.height >= max_tex_h)) {
RADEON_FALLBACK(("Source w/h too large (%d,%d).\n",
pSrcPixmap->drawable.width,
pSrcPixmap->drawable.height));
@@ -1522,8 +1962,8 @@ static Bool R600CheckComposite(int op, PicturePtr pSrcPicture, PicturePtr pMaskP
pDstPixmap = RADEONGetDrawablePixmap(pDstPicture->pDrawable);
- if (pDstPixmap->drawable.width >= max_dst_w ||
- pDstPixmap->drawable.height >= max_dst_h) {
+ if (unlikely(pDstPixmap->drawable.width >= max_dst_w ||
+ pDstPixmap->drawable.height >= max_dst_h)) {
RADEON_FALLBACK(("Dest w/h too large (%d,%d).\n",
pDstPixmap->drawable.width,
pDstPixmap->drawable.height));
@@ -1532,13 +1972,13 @@ static Bool R600CheckComposite(int op, PicturePtr pSrcPicture, PicturePtr pMaskP
if (pMaskPicture) {
PixmapPtr pMaskPixmap;
- if (!pMaskPicture->pDrawable)
+ if (unlikely(!pMaskPicture->pDrawable))
RADEON_FALLBACK(("Solid or gradient pictures not supported yet\n"));
pMaskPixmap = RADEONGetDrawablePixmap(pMaskPicture->pDrawable);
- if (pMaskPixmap->drawable.width >= max_tex_w ||
- pMaskPixmap->drawable.height >= max_tex_h) {
+ if (unlikely(pMaskPixmap->drawable.width >= max_tex_w ||
+ pMaskPixmap->drawable.height >= max_tex_h)) {
RADEON_FALLBACK(("Mask w/h too large (%d,%d).\n",
pMaskPixmap->drawable.width,
pMaskPixmap->drawable.height));
@@ -1549,9 +1989,9 @@ static Bool R600CheckComposite(int op, PicturePtr pSrcPicture, PicturePtr pMaskP
* on the source value. We can only get one of those into the
* single source value that we get to blend with.
*/
- if (R600BlendOp[op].src_alpha &&
+ if (unlikely(R600BlendOp[op].src_alpha &&
(R600BlendOp[op].blend_cntl & COLOR_SRCBLEND_mask) !=
- (BLEND_ZERO << COLOR_SRCBLEND_shift)) {
+ (BLEND_ZERO << COLOR_SRCBLEND_shift))) {
RADEON_FALLBACK(("Component alpha not supported with source "
"alpha and source value blending.\n"));
}
@@ -1579,12 +2019,13 @@ static Bool R600PrepareComposite(int op, PicturePtr pSrcPicture,
RADEONInfoPtr info = RADEONPTR(pScrn);
struct radeon_accel_state *accel_state = info->accel_state;
uint32_t blendcntl, dst_format;
- cb_config_t cb_conf;
- shader_config_t vs_conf, ps_conf;
+ uint32_t cb_color_info;
+/* cb_config_t cb_conf; */
+/* shader_config_t vs_conf, ps_conf; */
/* return FALSE; */
- if (pDst->drawable.bitsPerPixel < 8 || pSrc->drawable.bitsPerPixel < 8)
+ if (unlikely(pDst->drawable.bitsPerPixel < 8 || pSrc->drawable.bitsPerPixel < 8))
return FALSE;
if (pMask) {
@@ -1624,7 +2065,7 @@ static Bool R600PrepareComposite(int op, PicturePtr pSrcPicture,
radeon_add_pixmap(info->cs, pMask, RADEON_GEM_DOMAIN_GTT | RADEON_GEM_DOMAIN_VRAM, 0);
radeon_add_pixmap(info->cs, pDst, 0, RADEON_GEM_DOMAIN_VRAM);
ret = radeon_cs_space_check(info->cs);
- if (ret)
+ if (unlikely(ret))
RADEON_FALLBACK(("Not enough RAM to hw accel composite operation\n"));
} else
#endif
@@ -1632,18 +2073,18 @@ static Bool R600PrepareComposite(int op, PicturePtr pSrcPicture,
accel_state->dst_pitch = exaGetPixmapPitch(pDst) / (pDst->drawable.bitsPerPixel / 8);
accel_state->dst_size = exaGetPixmapPitch(pDst) * pDst->drawable.height;
- if (accel_state->dst_pitch & 7)
+ if (unlikely(accel_state->dst_pitch & 7))
RADEON_FALLBACK(("Bad dst pitch 0x%x\n", (int)accel_state->dst_pitch));
- if (accel_state->dst_mc_addr & 0xff)
+ if (unlikely(accel_state->dst_mc_addr & 0xff))
RADEON_FALLBACK(("Bad destination offset 0x%x\n", (int)accel_state->dst_mc_addr));
- if (!R600GetDestFormat(pDstPicture, &dst_format))
+ if (unlikely(!R600GetDestFormat(pDstPicture, &dst_format)))
return FALSE;
- CLEAR (cb_conf);
- CLEAR (vs_conf);
- CLEAR (ps_conf);
+/* CLEAR (cb_conf);
+ CLEAR (vs_conf);
+ CLEAR (ps_conf); */
if (pMask)
radeon_vbo_check(pScrn, 24);
@@ -1652,20 +2093,56 @@ static Bool R600PrepareComposite(int op, PicturePtr pSrcPicture,
r600_cp_start(pScrn);
- set_default_state(pScrn, accel_state->ib);
+ if (unlikely(!(accel_state->XInited3D))) set_default_state(pScrn, accel_state->ib);
- set_generic_scissor(pScrn, accel_state->ib, 0, 0, pDst->drawable.width, pDst->drawable.height);
+/* set_generic_scissor(pScrn, accel_state->ib, 0, 0, pDst->drawable.width, pDst->drawable.height);
set_screen_scissor(pScrn, accel_state->ib, 0, 0, pDst->drawable.width, pDst->drawable.height);
- set_window_scissor(pScrn, accel_state->ib, 0, 0, pDst->drawable.width, pDst->drawable.height);
- if (!R600TextureSetup(pSrcPicture, pSrc, 0)) {
+set_generic_scissor(ScrnInfoPtr pScrn, drmBufPtr ib, int x1, int y1, int x2, int y2)
+{
+ RADEONInfoPtr info = RADEONPTR(pScrn);
+*/
+ BEGIN_BATCH(18);
+ EREG(accel_state->ib, PA_SC_GENERIC_SCISSOR_TL, WINDOW_OFFSET_DISABLE_bit);
+ EREG(accel_state->ib, PA_SC_GENERIC_SCISSOR_BR, ((pDst->drawable.width << PA_SC_GENERIC_SCISSOR_BR__BR_X_shift) |
+ (pDst->drawable.height << PA_SC_GENERIC_SCISSOR_TL__TL_Y_shift)));
+/* END_BATCH();
+}
+*/
+/*
+set_screen_scissor(ScrnInfoPtr pScrn, drmBufPtr ib, int x1, int y1, int x2, int y2)
+{
+ RADEONInfoPtr info = RADEONPTR(pScrn);
+
+ BEGIN_BATCH(6); */
+ EREG(accel_state->ib, PA_SC_SCREEN_SCISSOR_TL, 0);
+ EREG(accel_state->ib, PA_SC_SCREEN_SCISSOR_BR, ((pDst->drawable.width << PA_SC_SCREEN_SCISSOR_BR__BR_X_shift) |
+ (pDst->drawable.height << PA_SC_SCREEN_SCISSOR_BR__BR_Y_shift)));
+/* END_BATCH();
+ } */
+
+
+
+/* set_window_scissor(pScrn, accel_state->ib, 0, 0, pDst->drawable.width, pDst->drawable.height);
+set_window_scissor(ScrnInfoPtr pScrn, drmBufPtr ib, int x1, int y1, int x2, int y2)
+{
+ RADEONInfoPtr info = RADEONPTR(pScrn);
+
+ BEGIN_BATCH(6); */
+ EREG(accel_state->ib, PA_SC_WINDOW_SCISSOR_TL, WINDOW_OFFSET_DISABLE_bit);
+ EREG(accel_state->ib, PA_SC_WINDOW_SCISSOR_BR, ((pDst->drawable.width << PA_SC_WINDOW_SCISSOR_BR__BR_X_shift) |
+ (pDst->drawable.height << PA_SC_WINDOW_SCISSOR_BR__BR_Y_shift)));
+ END_BATCH();
+/* } */
+
+ if (unlikely(!R600TextureSetup(pSrcPicture, pSrc, 0))) {
R600IBDiscard(pScrn, accel_state->ib);
r600_vb_discard(pScrn);
return FALSE;
}
if (pMask) {
- if (!R600TextureSetup(pMaskPicture, pMask, 1)) {
+ if (unlikely(!R600TextureSetup(pMaskPicture, pMask, 1))) {
R600IBDiscard(pScrn, accel_state->ib);
r600_vb_discard(pScrn);
return FALSE;
@@ -1707,31 +2184,65 @@ static Bool R600PrepareComposite(int op, PicturePtr pSrcPicture,
/* Shader */
/* flush SQ cache */
- cp_set_surface_sync(pScrn, accel_state->ib, SH_ACTION_ENA_bit,
- accel_state->vs_size, accel_state->vs_mc_addr,
- accel_state->shaders_bo, RADEON_GEM_DOMAIN_VRAM, 0);
-
- vs_conf.shader_addr = accel_state->vs_mc_addr;
+/* cp_set_surface_sync(pScrn, accel_state->ib, SH_ACTION_ENA_bit,
+ accel_state->vs_size, accel_state->vs_mc_addr,
+ accel_state->shaders_bo, RADEON_GEM_DOMAIN_VRAM, 0); */
+ BEGIN_BATCH(53);
+ /* PACK3(accel_state->ib, IT_SURFACE_SYNC, 4); */
+ E32X5((accel_state->ib), RADEON_CP_PACKET3 | ((IT_SURFACE_SYNC) << 8) | ((3 & 0x3fff) << 16),
+ /* E32(accel_state->ib, */ SH_ACTION_ENA_bit,
+ /* E32(accel_state->ib, */ ((512 + 255) >> 8),
+ /* E32(accel_state->ib, */ (accel_state->vs_mc_addr >> 8),
+ /* E32(accel_state->ib, */ 10); /* poll interval */
+ RELOC_BATCH(accel_state->shaders_bo, RADEON_GEM_DOMAIN_VRAM, 0);
+/* END_BATCH(); */
+
+/* vs_conf.shader_addr = accel_state->vs_mc_addr;
vs_conf.num_gprs = 3;
vs_conf.stack_size = 1;
vs_conf.bo = accel_state->shaders_bo;
- vs_setup (pScrn, accel_state->ib, &vs_conf, RADEON_GEM_DOMAIN_VRAM);
+ vs_setup (pScrn, accel_state->ib, &vs_conf, RADEON_GEM_DOMAIN_VRAM); */
- /* flush SQ cache */
- cp_set_surface_sync(pScrn, accel_state->ib, SH_ACTION_ENA_bit,
- accel_state->ps_size, accel_state->ps_mc_addr,
- accel_state->shaders_bo, RADEON_GEM_DOMAIN_VRAM, 0);
+/* BEGIN_BATCH(11); */
+ EREG(accel_state->ib, SQ_PGM_START_VS, accel_state->vs_mc_addr >> 8);
+ RELOC_BATCH(accel_state->shaders_bo, RADEON_GEM_DOMAIN_VRAM, 0);
+ EREG(accel_state->ib, SQ_PGM_RESOURCES_VS, ((3 << NUM_GPRS_shift) | (1 << STACK_SIZE_shift)));
+ EREG(accel_state->ib, SQ_PGM_CF_OFFSET_VS, 0);
+/* END_BATCH(); */
- ps_conf.shader_addr = accel_state->ps_mc_addr;
+ /* flush SQ cache */
+/* cp_set_surface_sync(pScrn, accel_state->ib, SH_ACTION_ENA_bit,
+ accel_state->ps_size, accel_state->ps_mc_addr,
+ accel_state->shaders_bo, RADEON_GEM_DOMAIN_VRAM, 0); */
+/* BEGIN_BATCH(30); */
+/* PACK3(accel_state->ib, IT_SURFACE_SYNC, 4); */
+ E32X5((accel_state->ib), RADEON_CP_PACKET3 | ((IT_SURFACE_SYNC) << 8) | ((3 & 0x3fff) << 16),
+ /* E32(accel_state->ib, */ SH_ACTION_ENA_bit,
+ /* E32(accel_state->ib, */ ((512 + 255) >> 8),
+ /* E32(accel_state->ib, */ (accel_state->ps_mc_addr >> 8),
+ /* E32(accel_state->ib, */ 10); /* poll interval */
+ RELOC_BATCH(accel_state->shaders_bo, RADEON_GEM_DOMAIN_VRAM, 0);
+/* END_BATCH(); */
+
+/* ps_conf.shader_addr = accel_state->ps_mc_addr;
ps_conf.num_gprs = 3;
ps_conf.stack_size = 0;
ps_conf.uncached_first_inst = 1;
ps_conf.clamp_consts = 0;
ps_conf.export_mode = 2;
ps_conf.bo = accel_state->shaders_bo;
- ps_setup (pScrn, accel_state->ib, &ps_conf, RADEON_GEM_DOMAIN_VRAM);
-
- BEGIN_BATCH(9);
+ ps_setup (pScrn, accel_state->ib, &ps_conf, RADEON_GEM_DOMAIN_VRAM); */
+
+/* BEGIN_BATCH(23); */
+ EREG(accel_state->ib, SQ_PGM_START_PS, accel_state->ps_mc_addr >> 8);
+ RELOC_BATCH(accel_state->shaders_bo, RADEON_GEM_DOMAIN_VRAM, 0);
+ EREG(accel_state->ib, SQ_PGM_RESOURCES_PS, ((3 << NUM_GPRS_shift) |
+ (UNCACHED_FIRST_INST_bit)));
+ EREG(accel_state->ib, SQ_PGM_EXPORTS_PS, 2);
+ EREG(accel_state->ib, SQ_PGM_CF_OFFSET_PS, 0);
+/* END_BATCH();
+
+ BEGIN_BATCH(9); */
EREG(accel_state->ib, CB_TARGET_MASK, (0xf << TARGET0_ENABLE_shift));
blendcntl = R600GetBlendCntl(op, pMaskPicture, pDstPicture->format);
@@ -1746,10 +2257,10 @@ static Bool R600PrepareComposite(int op, PicturePtr pSrcPicture,
PER_MRT_BLEND_bit));
EREG(accel_state->ib, CB_BLEND0_CONTROL, blendcntl);
}
- END_BATCH();
+/* END_BATCH(); */
- cb_conf.id = 0;
- cb_conf.w = accel_state->dst_pitch;
+ /* cb_conf.id = 0; */
+/* cb_conf.w = accel_state->dst_pitch;
cb_conf.h = pDst->drawable.height;
cb_conf.base = accel_state->dst_mc_addr;
cb_conf.format = dst_format;
@@ -1761,28 +2272,109 @@ static Bool R600PrepareComposite(int op, PicturePtr pSrcPicture,
case PICT_a1r5g5b5:
case PICT_x1r5g5b5:
default:
- cb_conf.comp_swap = 1; /* ARGB */
- break;
+ cb_conf.comp_swap = 1; */ /* ARGB */
+/* break;
case PICT_a8b8g8r8:
case PICT_x8b8g8r8:
- cb_conf.comp_swap = 0; /* ABGR */
- break;
+ cb_conf.comp_swap = 0; */ /* ABGR */
+/* break;
#ifdef PICT_TYPE_BGRA
case PICT_b8g8r8a8:
case PICT_b8g8r8x8:
- cb_conf.comp_swap = 3; /* BGRA */
- break;
+ cb_conf.comp_swap = 3; */ /* BGRA */
+/* break;
#endif
case PICT_r5g6b5:
- cb_conf.comp_swap = 2; /* RGB */
- break;
+ cb_conf.comp_swap = 2; */ /* RGB */
+/* break;
case PICT_a8:
- cb_conf.comp_swap = 3; /* A */
- break;
+ cb_conf.comp_swap = 3; */ /* A */
+/* break;
}
cb_conf.source_format = 1;
cb_conf.blend_clamp = 1;
- set_render_target(pScrn, accel_state->ib, &cb_conf, RADEON_GEM_DOMAIN_VRAM);
+ set_render_target(pScrn, accel_state->ib, &cb_conf, RADEON_GEM_DOMAIN_VRAM); */
+
+ switch (pDstPicture->format) {
+ case PICT_a8r8g8b8:
+ case PICT_x8r8g8b8:
+ case PICT_a1r5g5b5:
+ case PICT_x1r5g5b5:
+ default:
+ cb_color_info = (( dst_format << CB_COLOR0_INFO__FORMAT_shift) |
+ (1 << COMP_SWAP_shift) |
+ SOURCE_FORMAT_bit | BLEND_CLAMP_bit);
+ break;
+ case PICT_a8b8g8r8:
+ case PICT_x8b8g8r8:
+ cb_color_info = (( dst_format << CB_COLOR0_INFO__FORMAT_shift) |
+ (0 << COMP_SWAP_shift) |
+ SOURCE_FORMAT_bit | BLEND_CLAMP_bit);
+
+ break;
+#ifdef PICT_TYPE_BGRA
+ case PICT_b8g8r8a8:
+ case PICT_b8g8r8x8:
+ cb_color_info = (( dst_format << CB_COLOR0_INFO__FORMAT_shift) |
+ (3 << COMP_SWAP_shift) |
+ SOURCE_FORMAT_bit | BLEND_CLAMP_bit);
+ break;
+#endif
+ case PICT_r5g6b5:
+ cb_color_info = (( dst_format << CB_COLOR0_INFO__FORMAT_shift) |
+ (2 << COMP_SWAP_shift) |
+ SOURCE_FORMAT_bit | BLEND_CLAMP_bit);
+ break;
+ case PICT_a8:
+ cb_color_info = (( dst_format << CB_COLOR0_INFO__FORMAT_shift) |
+ (3 << COMP_SWAP_shift) |
+ SOURCE_FORMAT_bit | BLEND_CLAMP_bit);
+ break;
+ }
+
+
+
+ /* BEGIN_BATCH(3 + 2); */
+ EREG(accel_state->ib, (CB_COLOR0_BASE ), (accel_state->dst_mc_addr >> 8));
+ RELOC_BATCH(accel_state->dst_bo, 0, RADEON_GEM_DOMAIN_VRAM);
+ END_BATCH();
+
+ // rv6xx workaround
+ if ((info->ChipFamily > CHIP_FAMILY_R600) &&
+ (info->ChipFamily < CHIP_FAMILY_RV770)) {
+ BEGIN_BATCH(2);
+ /* PACK3(accel_state->ib, IT_SURFACE_BASE_UPDATE, 1); */
+ E32X2(accel_state->ib, RADEON_CP_PACKET3 | ((IT_SURFACE_BASE_UPDATE) << 8),
+ /* E32(accel_state->ib, */ 2 );
+ END_BATCH();
+ }
+ /* Set CMASK & TILE buffer to the offset of color buffer as
+ * we don't use those this shouldn't cause any issue and we
+ * then have a valid cmd stream
+ */
+ BEGIN_BATCH(22);
+ /* BEGIN_BATCH(3 + 2); */
+ EREG(accel_state->ib, (CB_COLOR0_TILE ), (0 >> 8)); // CMASK per-tile data base$
+ RELOC_BATCH(accel_state->dst_bo, 0, RADEON_GEM_DOMAIN_VRAM);
+ /* END_BATCH();
+ BEGIN_BATCH(3 + 2); */
+ EREG(accel_state->ib, (CB_COLOR0_FRAG ), (0 >> 8)); // FMASK per-tile data base$
+ RELOC_BATCH(accel_state->dst_bo, 0, RADEON_GEM_DOMAIN_VRAM);
+ /* END_BATCH();
+ BEGIN_BATCH(12); */
+ // pitch only for ARRAY_LINEAR_GENERAL, other tiling modes require addrlib
+ EREG(accel_state->ib, (CB_COLOR0_SIZE ), ((((accel_state->dst_pitch / 8) - 1) << PITCH_TILE_MAX_shift) |
+ ((((accel_state->dst_pitch * ((pDst->drawable.height + 7) & ~7)) / 64) - 1) << SLICE_TILE_MAX_shift)));
+ EREG(accel_state->ib, (CB_COLOR0_VIEW ), ((0 << SLICE_START_shift) |
+ (0 << SLICE_MAX_shift)));
+ EREG(accel_state->ib, (CB_COLOR0_INFO ), cb_color_info);
+ EREG(accel_state->ib, (CB_COLOR0_MASK ), ((0 << CMASK_BLOCK_MAX_shift) |
+ (0 << FMASK_TILE_MAX_shift)));
+ END_BATCH();
+
+
+
+
/* Interpolator setup */
BEGIN_BATCH(21);
@@ -1849,18 +2441,18 @@ static void R600Composite(PixmapPtr pDst,
vb[5] = (float)maskY;
vb[6] = (float)dstX;
- vb[7] = (float)(dstY + h);
+ vb[13] = vb[7] = (float)(dstY + h);
vb[8] = (float)srcX;
- vb[9] = (float)(srcY + h);
+ vb[15] = vb[9] = (float)(srcY + h);
vb[10] = (float)maskX;
- vb[11] = (float)(maskY + h);
+ vb[17] = vb[11] = (float)(maskY + h);
vb[12] = (float)(dstX + w);
- vb[13] = (float)(dstY + h);
+/* vb[13] = (float)(dstY + h);*/
vb[14] = (float)(srcX + w);
- vb[15] = (float)(srcY + h);
+/* vb[15] = (float)(srcY + h); */
vb[16] = (float)(maskX + w);
- vb[17] = (float)(maskY + h);
+/* vb[17] = (float)(maskY + h); */
radeon_vbo_commit(pScrn);
@@ -1874,14 +2466,14 @@ static void R600Composite(PixmapPtr pDst,
vb[3] = (float)srcY;
vb[4] = (float)dstX;
- vb[5] = (float)(dstY + h);
+ vb[9] = vb[5] = (float)(dstY + h);
vb[6] = (float)srcX;
- vb[7] = (float)(srcY + h);
+ vb[11] = vb[7] = (float)(srcY + h);
vb[8] = (float)(dstX + w);
- vb[9] = (float)(dstY + h);
+/* vb[9] = (float)(dstY + h); */
vb[10] = (float)(srcX + w);
- vb[11] = (float)(srcY + h);
+/* vb[11] = (float)(srcY + h); */
radeon_vbo_commit(pScrn);
}
@@ -1923,14 +2515,14 @@ R600CopyToVRAM(ScrnInfoPtr pScrn,
drmBufPtr scratch;
struct radeon_bo *bo = NULL;
- if (dst_pitch & 7)
+ if (unlikely(dst_pitch & 7))
return FALSE;
- if (dst_mc_addr & 0xff)
+ if (unlikely(dst_mc_addr & 0xff))
return FALSE;
scratch = RADEONCPGetBuffer(pScrn);
- if (scratch == NULL)
+ if (unlikely(scratch == NULL))
return FALSE;
scratch_mc_addr = info->gartLocation + info->dri->bufStart + (scratch->idx * scratch->total);
@@ -1950,7 +2542,7 @@ R600CopyToVRAM(ScrnInfoPtr pScrn,
h -= oldhpass;
temph = hpass = min(h, scratch->total/2 / scratch_pitch_bytes);
- if (hpass) {
+ if (likely(hpass)) {
scratch_offset = scratch->total/2 - scratch_offset;
dst = (char *)scratch->address + scratch_offset;
/* wait for the engine to be idle */
@@ -2016,16 +2608,16 @@ R600DownloadFromScreen(PixmapPtr pSrc, int x, int y, int w, int h,
struct radeon_bo *bo = NULL;
/* bad pipe setup in drm prior to 1.32 */
- if (info->dri->pKernelDRMVersion->version_minor < 32) {
- if ((info->ChipFamily == CHIP_FAMILY_RV740) && (w < 32 || h < 32))
+ if (unlikely(info->dri->pKernelDRMVersion->version_minor < 32)) {
+ if (unlikely((info->ChipFamily == CHIP_FAMILY_RV740) && (w < 32 || h < 32)))
return FALSE;
}
- if (src_pitch & 7)
+ if (unlikely(src_pitch & 7))
return FALSE;
scratch = RADEONCPGetBuffer(pScrn);
- if (scratch == NULL)
+ if (unlikely(scratch == NULL))
return FALSE;
scratch_mc_addr = info->gartLocation + info->dri->bufStart + (scratch->idx * scratch->total);
@@ -2048,7 +2640,7 @@ R600DownloadFromScreen(PixmapPtr pSrc, int x, int y, int w, int h,
y += oldhpass;
hpass = min(h, scratch->total/2 / scratch_pitch_bytes);
- if (hpass) {
+ if (likely(hpass)) {
scratch_offset = scratch->total/2 - scratch_offset;
/* blit from vram to scratch */
R600DoPrepareCopy(pScrn,
@@ -2062,7 +2654,7 @@ R600DownloadFromScreen(PixmapPtr pSrc, int x, int y, int w, int h,
}
/* wait for the engine to be idle */
- RADEONWaitForIdleCP(pScrn);
+ RADEONWaitForIdleCP(pScrn);
/* memcopy from scratch to sys */
while (oldhpass--) {
memcpy (dst, src, wpass);
@@ -2097,19 +2689,19 @@ R600UploadToScreenCS(PixmapPtr pDst, int x, int y, int w, int h,
Bool r;
int i;
- if (bpp < 8)
+ if (unlikely(bpp < 8))
return FALSE;
driver_priv = exaGetPixmapDriverPrivate(pDst);
/* If we know the BO won't be busy, don't bother */
- if (!radeon_bo_is_referenced_by_cs(driver_priv->bo, info->cs) &&
- !radeon_bo_is_busy(driver_priv->bo, &dst_domain))
+ if (unlikely(!radeon_bo_is_referenced_by_cs(driver_priv->bo, info->cs) &&
+ !radeon_bo_is_busy(driver_priv->bo, &dst_domain)))
return FALSE;
size = scratch_pitch * h;
scratch = radeon_bo_open(info->bufmgr, 0, size, 0, RADEON_GEM_DOMAIN_GTT, 0);
- if (scratch == NULL) {
+ if (unlikely(scratch == NULL)) {
return FALSE;
}
radeon_cs_space_reset_bos(info->cs);
@@ -2117,14 +2709,12 @@ R600UploadToScreenCS(PixmapPtr pDst, int x, int y, int w, int h,
RADEON_GEM_DOMAIN_VRAM, 0);
radeon_add_pixmap(info->cs, pDst, 0, RADEON_GEM_DOMAIN_VRAM);
radeon_cs_space_add_persistent_bo(info->cs, scratch, RADEON_GEM_DOMAIN_GTT, 0);
- r = radeon_cs_space_check(info->cs);
- if (r) {
+ if (unlikely(radeon_cs_space_check(info->cs))) {
r = FALSE;
goto out;
}
- r = radeon_bo_map(scratch, 0);
- if (r) {
+ if (unlikely(radeon_bo_map(scratch, 0))) {
r = FALSE;
goto out;
}
@@ -2170,7 +2760,7 @@ R600DownloadFromScreenCS(PixmapPtr pSrc, int x, int y, int w,
uint32_t src_pitch_hw = exaGetPixmapPitch(pSrc) / (bpp / 8);
Bool r;
- if (bpp < 8)
+ if (unlikely(bpp < 8))
return FALSE;
driver_priv = exaGetPixmapDriverPrivate(pSrc);
@@ -2186,12 +2776,12 @@ R600DownloadFromScreenCS(PixmapPtr pSrc, int x, int y, int w,
if (!src_domain)
radeon_bo_is_busy(driver_priv->bo, &src_domain);
- if (src_domain != RADEON_GEM_DOMAIN_VRAM)
+ if (unlikely(src_domain != RADEON_GEM_DOMAIN_VRAM))
return FALSE;
size = scratch_pitch * h;
scratch = radeon_bo_open(info->bufmgr, 0, size, 0, RADEON_GEM_DOMAIN_GTT, 0);
- if (scratch == NULL) {
+ if (unlikely(scratch == NULL)) {
return FALSE;
}
radeon_cs_space_reset_bos(info->cs);
@@ -2199,8 +2789,7 @@ R600DownloadFromScreenCS(PixmapPtr pSrc, int x, int y, int w,
RADEON_GEM_DOMAIN_VRAM, 0);
radeon_add_pixmap(info->cs, pSrc, RADEON_GEM_DOMAIN_GTT | RADEON_GEM_DOMAIN_VRAM, 0);
radeon_cs_space_add_persistent_bo(info->cs, scratch, 0, RADEON_GEM_DOMAIN_GTT);
- r = radeon_cs_space_check(info->cs);
- if (r) {
+ if (unlikely(radeon_cs_space_check(info->cs))) {
r = FALSE;
goto out;
}
@@ -2218,8 +2807,7 @@ R600DownloadFromScreenCS(PixmapPtr pSrc, int x, int y, int w,
if (info->cs)
radeon_cs_flush_indirect(pScrn);
- r = radeon_bo_map(scratch, 0);
- if (r) {
+ if (radeon_bo_map(scratch, 0)) {
r = FALSE;
goto out;
}
@@ -2284,7 +2872,7 @@ R600AllocShaders(ScrnInfoPtr pScrn, ScreenPtr pScreen)
if (info->cs) {
accel_state->shaders_bo = radeon_bo_open(info->bufmgr, 0, size, 0,
RADEON_GEM_DOMAIN_VRAM, 0);
- if (accel_state->shaders_bo == NULL) {
+ if (unlikely(accel_state->shaders_bo == NULL)) {
ErrorF("Allocating shader failed\n");
return FALSE;
}
@@ -2296,7 +2884,7 @@ R600AllocShaders(ScrnInfoPtr pScrn, ScreenPtr pScreen)
accel_state->shaders = exaOffscreenAlloc(pScreen, size, 256,
TRUE, NULL, NULL);
- if (accel_state->shaders == NULL)
+ if (unlikely(accel_state->shaders == NULL))
return FALSE;
}
@@ -2316,7 +2904,7 @@ R600LoadShaders(ScrnInfoPtr pScrn)
if (info->cs) {
ret = radeon_bo_map(accel_state->shaders_bo, 1);
- if (ret) {
+ if (unlikely(ret)) {
FatalError("failed to map shader %d\n", ret);
return FALSE;
}
diff --git a/src/r600_state.h b/src/r600_state.h
index 1f2fbaa..4893924 100644
--- a/src/r600_state.h
+++ b/src/r600_state.h
@@ -8,6 +8,16 @@ typedef int bool_t;
#define CLEAR(x) memset (&x, 0, sizeof(x))
+#ifndef likely
+#define likely(x) __builtin_expect((x),1)
+#endif
+
+#ifndef unlikely
+#define unlikely(x) __builtin_expect((x),0)
+#endif
+
+
+
/* Sequencer / thread handling */
typedef struct {
int ps_prio;
@@ -179,9 +189,18 @@ typedef struct {
#if defined(XF86DRM_MODE)
#define BEGIN_BATCH(n) \
do { \
- if (info->cs) \
- radeon_ddx_cs_start(pScrn, (n), __FILE__, __func__, __LINE__); \
+ if (info->cs) { \
+ if (unlikely(info->cs->cdw + (n) > info->cs->ndw)) { \
+ radeon_cs_flush_indirect(pScrn); \
+ } \
+ radeon_cs_begin(info->cs, (n), __FILE__, __func__, __LINE__); \
+ } \
} while(0)
+
+/* radeon_ddx_cs_start(pScrn, (n), __FILE__, __func__, __LINE__); \ */
+
+
+
#define END_BATCH() \
do { \
if (info->cs) \
@@ -192,7 +211,7 @@ do { \
if (info->cs) { \
int _ret; \
_ret = radeon_cs_write_reloc(info->cs, (bo), (rd), (wd), 0); \
- if (_ret) ErrorF("reloc emit failure %d (%s %d)\n", _ret, __func__, __LINE__); \
+ if (unlikely(_ret)) ErrorF("reloc emit failure %d (%s %d)\n", _ret, __func__, __LINE__); \
} \
} while(0)
#define E32(ib, dword) \
@@ -205,6 +224,295 @@ do { \
(ib)->used += 4; \
} \
} while (0)
+
+#define E32X2(ib, dword1, dword2) \
+do { \
+ if (info->cs) { \
+ radeon_cs_write_two_dwords(info->cs, (dword1), (dword2)); \
+ } else { \
+ uint32_t __indx = ((ib)->used) >> 2; \
+ uint32_t *ib_head = (pointer)(char*)(ib)->address; \
+ ib_head[__indx] = (dword1); \
+ ib_head[__indx + 1] = (dword2); \
+ (ib)->used += 8; \
+ } \
+} while (0)
+
+#define E32X3(ib, dword1, dword2, dword3) \
+do { \
+ if (info->cs) { \
+ radeon_cs_write_three_dwords(info->cs, (dword1), (dword2),(dword3)); \
+ } else { \
+ uint32_t __indx = ((ib)->used) >> 2; \
+ uint32_t *ib_head = (pointer)(char*)(ib)->address; \
+ ib_head[__indx] = (dword1); \
+ ib_head[__indx + 1] = (dword2); \
+ ib_head[__indx + 2] = (dword3); \
+ (ib)->used += 12; \
+ } \
+} while (0)
+
+#define E32X4(ib, dword1, dword2, dword3, dword4) \
+do { \
+ if (info->cs) { \
+ radeon_cs_write_four_dwords(info->cs, (dword1), (dword2),(dword3),(dword4)); \
+ } else { \
+ uint32_t __indx = ((ib)->used) >> 2; \
+ uint32_t *ib_head = (pointer)(char*)(ib)->address; \
+ ib_head[__indx] = (dword1); \
+ ib_head[__indx + 1] = (dword2); \
+ ib_head[__indx + 2] = (dword3); \
+ ib_head[__indx + 3] = (dword4); \
+ (ib)->used += 16; \
+ } \
+} while (0)
+
+
+#define E32X5(ib, dword1, dword2, dword3, dword4, dword5) \
+do { \
+ if (info->cs) { \
+ radeon_cs_write_five_dwords(info->cs, (dword1), (dword2),(dword3),(dword4), (dword5)); \
+ } else { \
+ uint32_t __indx = ((ib)->used) >> 2; \
+ uint32_t *ib_head = (pointer)(char*)(ib)->address; \
+ ib_head[__indx] = (dword1); \
+ ib_head[__indx + 1] = (dword2); \
+ ib_head[__indx + 2] = (dword3); \
+ ib_head[__indx + 3] = (dword4); \
+ ib_head[__indx + 4] = (dword5); \
+ (ib)->used += 20; \
+ } \
+} while (0)
+
+#define E32X6(ib, dword1, dword2, dword3, dword4, dword5, dword6) \
+do { \
+ if (info->cs) { \
+ radeon_cs_write_six_dwords(info->cs, (dword1), (dword2),(dword3),(dword4), (dword5), (dword6)); \
+ } else { \
+ uint32_t __indx = ((ib)->used) >> 2; \
+ uint32_t *ib_head = (pointer)(char*)(ib)->address; \
+ ib_head[__indx] = (dword1); \
+ ib_head[__indx + 1] = (dword2); \
+ ib_head[__indx + 2] = (dword3); \
+ ib_head[__indx + 3] = (dword4); \
+ ib_head[__indx + 4] = (dword5); \
+ ib_head[__indx + 5] = (dword6); \
+ (ib)->used += 24; \
+ } \
+} while (0)
+
+#define E32X7(ib, dword1, dword2, dword3, dword4, dword5, dword6, dword7) \
+do { \
+ if (info->cs) { \
+ radeon_cs_write_seven_dwords(info->cs, (dword1), (dword2),(dword3),(dword4), (dword5), (dword6), (dword7)); \
+ } else { \
+ uint32_t __indx = ((ib)->used) >> 2; \
+ uint32_t *ib_head = (pointer)(char*)(ib)->address; \
+ ib_head[__indx] = (dword1); \
+ ib_head[__indx + 1] = (dword2); \
+ ib_head[__indx + 2] = (dword3); \
+ ib_head[__indx + 3] = (dword4); \
+ ib_head[__indx + 4] = (dword5); \
+ ib_head[__indx + 5] = (dword6); \
+ ib_head[__indx + 6] = (dword7); \
+ (ib)->used += 28; \
+ } \
+} while (0)
+
+
+
+#define PACK3(ib, cmd, num) \
+do { \
+ E32((ib), RADEON_CP_PACKET3 | ((cmd) << 8) | ((((num) - 1) & 0x3fff) << 16)); \
+} while (0)
+
+/* write num registers, start at reg */
+/* If register falls in a special area, special commands are issued */
+#define PACK0(ib, reg, num) \
+do { \
+ if (info->cs) { \
+ if ((reg) >= SET_CONFIG_REG_offset && (reg) < SET_CONFIG_REG_end) { \
+ radeon_cs_write_two_dwords(info->cs, (RADEON_CP_PACKET3 | ((IT_SET_CONFIG_REG) << 8) | (((num) & 0x3fff) << 16)), \
+ /* radeon_cs_write_dword(info->cs,*/ (((reg) - SET_CONFIG_REG_offset) >> 2)); \
+ } else if ((reg) >= SET_CONTEXT_REG_offset && (reg) < SET_CONTEXT_REG_end) { \
+ radeon_cs_write_two_dwords(info->cs, (RADEON_CP_PACKET3 | ((IT_SET_CONTEXT_REG) << 8) | (((num) & 0x3fff) << 16)), \
+ /* radeon_cs_write_dword(info->cs,*/ (((reg) - SET_CONTEXT_REG_offset) >> 2)); \
+ } else if ((reg) >= SET_ALU_CONST_offset && (reg) < SET_ALU_CONST_end) { \
+ radeon_cs_write_two_dwords(info->cs, (RADEON_CP_PACKET3 | ((IT_SET_ALU_CONST) << 8) | (((num) & 0x3fff) << 16)), \
+ /* radeon_cs_write_dword(info->cs, */ (((reg) - SET_ALU_CONST_offset) >> 2)); \
+ } else if ((reg) >= SET_RESOURCE_offset && (reg) < SET_RESOURCE_end) { \
+ radeon_cs_write_two_dwords(info->cs, (RADEON_CP_PACKET3 | ((IT_SET_RESOURCE) << 8) | (((num) & 0x3fff) << 16)), \
+ /* radeon_cs_write_dword(info->cs, */ (((reg) - SET_RESOURCE_offset) >> 2)); \
+ } else if ((reg) >= SET_SAMPLER_offset && (reg) < SET_SAMPLER_end) { \
+ radeon_cs_write_two_dwords(info->cs, (RADEON_CP_PACKET3 | ((IT_SET_SAMPLER) << 8) | (((num) & 0x3fff) << 16)), \
+ /* radeon_cs_write_dword(info->cs, */ (((reg) - SET_SAMPLER_offset) >> 2)); \
+ } else if ((reg) >= SET_CTL_CONST_offset && (reg) < SET_CTL_CONST_end) { \
+ radeon_cs_write_two_dwords(info->cs, (RADEON_CP_PACKET3 | ((IT_SET_CTL_CONST) << 8) | (((num) & 0x3fff) << 16)), \
+ /* radeon_cs_write_dword(info->cs, */ (((reg) - SET_CTL_CONST_offset) >> 2)); \
+ } else if ((reg) >= SET_LOOP_CONST_offset && (reg) < SET_LOOP_CONST_end) { \
+ radeon_cs_write_two_dwords(info->cs, (RADEON_CP_PACKET3 | ((IT_SET_LOOP_CONST) << 8) | (((num) & 0x3fff) << 16)), \
+ /* radeon_cs_write_dword(info->cs, */ (((reg) - SET_LOOP_CONST_offset) >> 2)); \
+ } else if ((reg) >= SET_BOOL_CONST_offset && (reg) < SET_BOOL_CONST_end) { \
+ radeon_cs_write_two_dwords(info->cs, (RADEON_CP_PACKET3 | ((IT_SET_BOOL_CONST) << 8) | (((num) & 0x3fff) << 16)), \
+ /* radeon_cs_write_dword(info->cs, */ (((reg) - SET_BOOL_CONST_offset) >> 2)); \
+ } else { \
+ radeon_cs_write_dword(info->cs, CP_PACKET0 ((reg), (num) - 1)); \
+ } \
+ } else { \
+ uint32_t __indx = ((ib)->used) >> 2; \
+ uint32_t *ib_head = (pointer)(char*)(ib)->address; \
+ (ib)->used += 8; \
+ if ((reg) >= SET_CONFIG_REG_offset && (reg) < SET_CONFIG_REG_end) { \
+ ib_head[__indx] = ((RADEON_CP_PACKET3 | ((IT_SET_CONFIG_REG) << 8) | (((num) & 0x3fff) << 16))); \
+ ib_head[__indx + 1] = (((reg) - SET_CONFIG_REG_offset) >> 2); \
+ } else if ((reg) >= SET_CONTEXT_REG_offset && (reg) < SET_CONTEXT_REG_end) { \
+ ib_head[__indx] = ((RADEON_CP_PACKET3 | ((IT_SET_CONTEXT_REG) << 8) | (((num) & 0x3fff) << 16))); \
+ ib_head[__indx + 1] = (((reg) - SET_CONTEXT_REG_offset) >> 2); \
+ } else if ((reg) >= SET_ALU_CONST_offset && (reg) < SET_ALU_CONST_end) { \
+ ib_head[__indx] = ((RADEON_CP_PACKET3 | ((IT_SET_ALU_CONST) << 8) | (((num) & 0x3fff) << 16))); \
+ ib_head[__indx + 1] = (((reg) - SET_ALU_CONST_offset) >> 2); \
+ } else if ((reg) >= SET_RESOURCE_offset && (reg) < SET_RESOURCE_end) { \
+ ib_head[__indx] = ((RADEON_CP_PACKET3 | ((IT_SET_RESOURCE) << 8) | (((num) & 0x3fff) << 16))); \
+ ib_head[__indx + 1] = (((reg) - SET_RESOURCE_offset) >> 2); \
+ } else if ((reg) >= SET_SAMPLER_offset && (reg) < SET_SAMPLER_end) { \
+ ib_head[__indx] = ((RADEON_CP_PACKET3 | ((IT_SET_SAMPLER) << 8) | (((num) & 0x3fff) << 16))); \
+ ib_head[__indx + 1] = (((reg) - SET_SAMPLER_offset) >> 2); \
+ } else if ((reg) >= SET_CTL_CONST_offset && (reg) < SET_CTL_CONST_end) { \
+ ib_head[__indx] = ((RADEON_CP_PACKET3 | ((IT_SET_CTL_CONST) << 8) | (((num) & 0x3fff) << 16))); \
+ ib_head[__indx + 1] = (((reg) - SET_CTL_CONST_offset) >> 2); \
+ } else if ((reg) >= SET_LOOP_CONST_offset && (reg) < SET_LOOP_CONST_end) { \
+ ib_head[__indx] = ((RADEON_CP_PACKET3 | ((IT_SET_LOOP_CONST) << 8) | (((num) & 0x3fff) << 16))); \
+ ib_head[__indx + 1] = (((reg) - SET_LOOP_CONST_offset) >> 2); \
+ } else if ((reg) >= SET_BOOL_CONST_offset && (reg) < SET_BOOL_CONST_end) { \
+ ib_head[__indx] = ((RADEON_CP_PACKET3 | ((IT_SET_BOOL_CONST) << 8) | (((num) & 0x3fff) << 16))); \
+ ib_head[__indx + 1] = (((reg) - SET_BOOL_CONST_offset) >> 2); \
+ } else { \
+ ib_head[__indx] = (CP_PACKET0 ((reg), (num) - 1)); \
+ (ib)->used -= 4; \
+ } \
+ } \
+} while (0)
+
+/* write a single register */
+#define EREG(ib, reg, val) \
+do { \
+ if (info->cs) { \
+ if ((reg) >= SET_CONFIG_REG_offset && (reg) < SET_CONFIG_REG_end) { \
+ info->cs->packets[info->cs->cdw] = (RADEON_CP_PACKET3 | ((IT_SET_CONFIG_REG) << 8) | (((1) & 0x3fff) << 16)); \
+ info->cs->packets[info->cs->cdw + 1] = (((reg) - SET_CONFIG_REG_offset) >> 2); \
+ info->cs->packets[info->cs->cdw + 2] = val; \
+ info->cs->cdw += 3; \
+ if (info->cs->section_ndw) { \
+ info->cs->section_cdw += 3; \
+ } \
+ } else if ((reg) >= SET_CONTEXT_REG_offset && (reg) < SET_CONTEXT_REG_end) { \
+ info->cs->packets[info->cs->cdw] = (RADEON_CP_PACKET3 | ((IT_SET_CONTEXT_REG) << 8) | (((1) & 0x3fff) << 16)); \
+ info->cs->packets[info->cs->cdw + 1] = (((reg) - SET_CONTEXT_REG_offset) >> 2); \
+ info->cs->packets[info->cs->cdw + 2] = val; \
+ info->cs->cdw += 3; \
+ if (info->cs->section_ndw) { \
+ info->cs->section_cdw += 3; \
+ } \
+ } else if ((reg) >= SET_ALU_CONST_offset && (reg) < SET_ALU_CONST_end) { \
+ info->cs->packets[info->cs->cdw] = (RADEON_CP_PACKET3 | ((IT_SET_ALU_CONST) << 8) | (((1) & 0x3fff) << 16)); \
+ info->cs->packets[info->cs->cdw + 1] = (((reg) - SET_ALU_CONST_offset) >> 2); \
+ info->cs->packets[info->cs->cdw + 2] = val; \
+ info->cs->cdw += 3; \
+ if (info->cs->section_ndw) { \
+ info->cs->section_cdw += 3; \
+ } \
+ } else if ((reg) >= SET_RESOURCE_offset && (reg) < SET_RESOURCE_end) { \
+ info->cs->packets[info->cs->cdw] = (RADEON_CP_PACKET3 | ((IT_SET_RESOURCE) << 8) | (((1) & 0x3fff) << 16)); \
+ info->cs->packets[info->cs->cdw + 1] = (((reg) - SET_RESOURCE_offset) >> 2); \
+ info->cs->packets[info->cs->cdw + 2] = val; \
+ info->cs->cdw += 3; \
+ if (info->cs->section_ndw) { \
+ info->cs->section_cdw += 3; \
+ } \
+ } else if ((reg) >= SET_SAMPLER_offset && (reg) < SET_SAMPLER_end) { \
+ info->cs->packets[info->cs->cdw] = (RADEON_CP_PACKET3 | ((IT_SET_SAMPLER) << 8) | (((1) & 0x3fff) << 16)); \
+ info->cs->packets[info->cs->cdw + 1] = (((reg) - SET_SAMPLER_offset) >> 2); \
+ info->cs->packets[info->cs->cdw + 2] = val; \
+ info->cs->cdw += 3; \
+ if (info->cs->section_ndw) { \
+ info->cs->section_cdw += 3; \
+ } \
+ } else if ((reg) >= SET_CTL_CONST_offset && (reg) < SET_CTL_CONST_end) { \
+ info->cs->packets[info->cs->cdw] = (RADEON_CP_PACKET3 | ((IT_SET_CTL_CONST) << 8) | (((1) & 0x3fff) << 16)); \
+ info->cs->packets[info->cs->cdw + 1] = (((reg) - SET_CTL_CONST_offset) >> 2); \
+ info->cs->packets[info->cs->cdw + 2] = val; \
+ info->cs->cdw += 3; \
+ if (info->cs->section_ndw) { \
+ info->cs->section_cdw += 3; \
+ } \
+ } else if ((reg) >= SET_LOOP_CONST_offset && (reg) < SET_LOOP_CONST_end) { \
+ info->cs->packets[info->cs->cdw] = (RADEON_CP_PACKET3 | ((IT_SET_LOOP_CONST) << 8) | (((1) & 0x3fff) << 16)); \
+ info->cs->packets[info->cs->cdw + 1] = (((reg) - SET_LOOP_CONST_offset) >> 2); \
+ info->cs->packets[info->cs->cdw + 2] = val; \
+ info->cs->cdw += 3; \
+ if (info->cs->section_ndw) { \
+ info->cs->section_cdw += 3; \
+ } \
+ } else if ((reg) >= SET_BOOL_CONST_offset && (reg) < SET_BOOL_CONST_end) { \
+ info->cs->packets[info->cs->cdw] = (RADEON_CP_PACKET3 | ((IT_SET_BOOL_CONST) << 8) | (((1) & 0x3fff) << 16)); \
+ info->cs->packets[info->cs->cdw + 1] = (((reg) - SET_BOOL_CONST_offset) >> 2); \
+ info->cs->packets[info->cs->cdw + 2] = val; \
+ info->cs->cdw += 3; \
+ if (info->cs->section_ndw) { \
+ info->cs->section_cdw += 3; \
+ } \
+ } else { \
+ info->cs->packets[info->cs->cdw] = CP_PACKET0((reg), 0); \
+ info->cs->packets[info->cs->cdw + 1] = val; \
+ info->cs->cdw += 2; \
+ if (info->cs->section_ndw) { \
+ info->cs->section_cdw += 2; \
+ } \
+ } \
+ } else { \
+ uint32_t __indx = ((ib)->used) >> 2; \
+ uint32_t *ib_head = (pointer)(char*)(ib)->address; \
+ (ib)->used += 12; \
+ if ((reg) >= SET_CONFIG_REG_offset && (reg) < SET_CONFIG_REG_end) { \
+ ib_head[__indx] = ((RADEON_CP_PACKET3 | ((IT_SET_CONFIG_REG) << 8) | (((1) & 0x3fff) << 16))); \
+ ib_head[__indx + 1] = (((reg) - SET_CONFIG_REG_offset) >> 2); \
+ ib_head[__indx + 2] = val; \
+ } else if ((reg) >= SET_CONTEXT_REG_offset && (reg) < SET_CONTEXT_REG_end) { \
+ ib_head[__indx] = ((RADEON_CP_PACKET3 | ((IT_SET_CONTEXT_REG) << 8) | (((1) & 0x3fff) << 16))); \
+ ib_head[__indx + 1] = (((reg) - SET_CONTEXT_REG_offset) >> 2); \
+ ib_head[__indx + 2] = val; \
+ } else if ((reg) >= SET_ALU_CONST_offset && (reg) < SET_ALU_CONST_end) { \
+ ib_head[__indx] = ((RADEON_CP_PACKET3 | ((IT_SET_ALU_CONST) << 8) | (((1) & 0x3fff) << 16))); \
+ ib_head[__indx + 1] = (((reg) - SET_ALU_CONST_offset) >> 2); \
+ ib_head[__indx + 2] = val; \
+ } else if ((reg) >= SET_RESOURCE_offset && (reg) < SET_RESOURCE_end) { \
+ ib_head[__indx] = ((RADEON_CP_PACKET3 | ((IT_SET_RESOURCE) << 8) | (((1) & 0x3fff) << 16))); \
+ ib_head[__indx + 1] = (((reg) - SET_RESOURCE_offset) >> 2); \
+ ib_head[__indx + 2] = val; \
+ } else if ((reg) >= SET_SAMPLER_offset && (reg) < SET_SAMPLER_end) { \
+ ib_head[__indx] = ((RADEON_CP_PACKET3 | ((IT_SET_SAMPLER) << 8) | (((1) & 0x3fff) << 16))); \
+ ib_head[__indx + 1] = (((reg) - SET_SAMPLER_offset) >> 2); \
+ ib_head[__indx + 2] = val; \
+ } else if ((reg) >= SET_CTL_CONST_offset && (reg) < SET_CTL_CONST_end) { \
+ ib_head[__indx] = ((RADEON_CP_PACKET3 | ((IT_SET_CTL_CONST) << 8) | (((1) & 0x3fff) << 16))); \
+ ib_head[__indx + 1] = (((reg) - SET_CTL_CONST_offset) >> 2); \
+ ib_head[__indx + 2] = val; \
+ } else if ((reg) >= SET_LOOP_CONST_offset && (reg) < SET_LOOP_CONST_end) { \
+ ib_head[__indx] = ((RADEON_CP_PACKET3 | ((IT_SET_LOOP_CONST) << 8) | (((1) & 0x3fff) << 16))); \
+ ib_head[__indx + 1] = (((reg) - SET_LOOP_CONST_offset) >> 2); \
+ ib_head[__indx + 2] = val; \
+ } else if ((reg) >= SET_BOOL_CONST_offset && (reg) < SET_BOOL_CONST_end) { \
+ ib_head[__indx] = ((RADEON_CP_PACKET3 | ((IT_SET_BOOL_CONST) << 8) | ((1) << 16))); \
+ ib_head[__indx + 1] = (((reg) - SET_BOOL_CONST_offset) >> 2); \
+ ib_head[__indx + 2] = val; \
+ } else { \
+ ib_head[__indx] = (CP_PACKET0 ((reg), 0)); \
+ ib_head[__indx + 1] = val; \
+ (ib)->used -= 4; \
+ } \
+ } \
+} while (0)
+
#else
#define BEGIN_BATCH(n) do {(void)info;} while(0)
#define END_BATCH() do {} while(0)
@@ -215,15 +523,79 @@ do { \
ib_head[(ib)->used >> 2] = (dword); \
(ib)->used += 4; \
} while (0)
-#endif
-#define EFLOAT(ib, val) \
-do { \
- union { float f; uint32_t d; } a; \
- a.f = (val); \
- E32((ib), a.d); \
+#define E32X2(ib, dword1, dword2) \
+do { \
+ uint32_t __indx = ((ib)->used) >> 2; \
+ uint32_t *ib_head = (pointer)(char*)(ib)->address; \
+ ib_head[__indx] = (dword1); \
+ ib_head[__indx + 1] = (dword2); \
+ (ib)->used += 8; \
+} while (0)
+
+#define E32X3(ib, dword1, dword2, dword3) \
+do { \
+ uint32_t __indx = ((ib)->used) >> 2; \
+ uint32_t *ib_head = (pointer)(char*)(ib)->address; \
+ ib_head[__indx] = (dword1); \
+ ib_head[__indx + 1] = (dword2); \
+ ib_head[__indx + 2] = (dword3); \
+ (ib)->used += 12; \
+} while (0)
+
+#define E32X4(ib, dword1, dword2, dword3, dword4) \
+do { \
+ uint32_t __indx = ((ib)->used) >> 2; \
+ uint32_t *ib_head = (pointer)(char*)(ib)->address; \
+ ib_head[__indx] = (dword1); \
+ ib_head[__indx + 1] = (dword2); \
+ ib_head[__indx + 2] = (dword3); \
+ ib_head[__indx + 3] = (dword4); \
+ (ib)->used += 16; \
} while (0)
+#define E32X5(ib, dword1, dword2, dword3, dword4, dword5) \
+do { \
+ uint32_t __indx = ((ib)->used) >> 2; \
+ uint32_t *ib_head = (pointer)(char*)(ib)->address; \
+ ib_head[__indx] = (dword1); \
+ ib_head[__indx + 1] = (dword2); \
+ ib_head[__indx + 2] = (dword3); \
+ ib_head[__indx + 3] = (dword4); \
+ ib_head[__indx + 4] = (dword5); \
+ (ib)->used += 20; \
+} while (0)
+
+
+
+#define E32X6(ib, dword1, dword2, dword3, dword4, dword5, dword6) \
+do { \
+ uint32_t __indx = ((ib)->used) >> 2; \
+ uint32_t *ib_head = (pointer)(char*)(ib)->address; \
+ ib_head[__indx] = (dword1); \
+ ib_head[__indx + 1] = (dword2); \
+ ib_head[__indx + 2] = (dword3); \
+ ib_head[__indx + 3] = (dword4); \
+ ib_head[__indx + 4] = (dword5); \
+ ib_head[__indx + 5] = (dword6); \
+ (ib)->used += 24; \
+} while (0)
+
+#define E32X7(ib, dword1, dword2, dword3, dword4, dword5, dword6, dword7) \
+do { \
+ uint32_t __indx = ((ib)->used) >> 2; \
+ uint32_t *ib_head = (pointer)(char*)(ib)->address; \
+ ib_head[__indx] = (dword1); \
+ ib_head[__indx + 1] = (dword2); \
+ ib_head[__indx + 2] = (dword3); \
+ ib_head[__indx + 3] = (dword4); \
+ ib_head[__indx + 4] = (dword5); \
+ ib_head[__indx + 5] = (dword6); \
+ ib_head[__indx + 6] = (dword7); \
+ (ib)->used += 28; \
+} while (0)
+
+
#define PACK3(ib, cmd, num) \
do { \
E32((ib), RADEON_CP_PACKET3 | ((cmd) << 8) | ((((num) - 1) & 0x3fff) << 16)); \
@@ -269,6 +641,17 @@ do { \
E32((ib), (val)); \
} while (0)
+
+#endif
+
+#define EFLOAT(ib, val) \
+do { \
+ union { float f; uint32_t d; } a; \
+ a.f = (val); \
+ E32((ib), a.d); \
+} while (0)
+
+
void R600CPFlushIndirect(ScrnInfoPtr pScrn, drmBufPtr ib);
void R600IBDiscard(ScrnInfoPtr pScrn, drmBufPtr ib);
diff --git a/src/r600_textured_videofuncs.c b/src/r600_textured_videofuncs.c
index 7b55cec..79e0631 100644
--- a/src/r600_textured_videofuncs.c
+++ b/src/r600_textured_videofuncs.c
@@ -74,7 +74,8 @@ R600DisplayTexturedVideo(ScrnInfoPtr pScrn, RADEONPortPrivPtr pPriv)
cb_config_t cb_conf;
tex_resource_t tex_res;
tex_sampler_t tex_samp;
- shader_config_t vs_conf, ps_conf;
+ shader_config_t ps_conf;
+/* shader_config_t vs_conf, ps_conf; */
/*
* y' = y - .0625
* u' = u - .5
@@ -165,7 +166,7 @@ R600DisplayTexturedVideo(ScrnInfoPtr pScrn, RADEONPortPrivPtr pPriv)
CLEAR (cb_conf);
CLEAR (tex_res);
CLEAR (tex_samp);
- CLEAR (vs_conf);
+/* CLEAR (vs_conf); */
CLEAR (ps_conf);
#if defined(XF86DRM_MODE)
@@ -249,20 +250,51 @@ R600DisplayTexturedVideo(ScrnInfoPtr pScrn, RADEONPortPrivPtr pPriv)
/* Shader */
/* flush SQ cache */
- cp_set_surface_sync(pScrn, accel_state->ib, SH_ACTION_ENA_bit,
+/* cp_set_surface_sync(pScrn, accel_state->ib, SH_ACTION_ENA_bit,
accel_state->vs_size, accel_state->vs_mc_addr,
- accel_state->shaders_bo, RADEON_GEM_DOMAIN_VRAM, 0);
+ accel_state->shaders_bo, RADEON_GEM_DOMAIN_VRAM, 0); */
+ BEGIN_BATCH(7);
+ /*PACK3(accel_state->ib, IT_SURFACE_SYNC, 4); */
+ E32X5((accel_state->ib), RADEON_CP_PACKET3 | ((IT_SURFACE_SYNC) << 8) | ((3 & 0x3fff) << 16),
+ SH_ACTION_ENA_bit,
+ ((512 + 255) >> 8),
+ (accel_state->vs_mc_addr >> 8),
+ 10); /* poll interval */
+ RELOC_BATCH(accel_state->shaders_bo, RADEON_GEM_DOMAIN_VRAM, 0);
+ END_BATCH();
- vs_conf.shader_addr = accel_state->vs_mc_addr;
+
+
+/* vs_conf.shader_addr = accel_state->vs_mc_addr;
vs_conf.num_gprs = 2;
vs_conf.stack_size = 0;
vs_conf.bo = accel_state->shaders_bo;
- vs_setup (pScrn, accel_state->ib, &vs_conf, RADEON_GEM_DOMAIN_VRAM);
+ vs_setup (pScrn, accel_state->ib, &vs_conf, RADEON_GEM_DOMAIN_VRAM); */
+
+ BEGIN_BATCH(11);
+ EREG(accel_state->ib, SQ_PGM_START_VS, accel_state->vs_mc_addr >> 8);
+ RELOC_BATCH(accel_state->shaders_bo, RADEON_GEM_DOMAIN_VRAM, 0);
+ EREG(accel_state->ib, SQ_PGM_RESOURCES_VS, 2 << NUM_GPRS_shift);
+ EREG(accel_state->ib, SQ_PGM_CF_OFFSET_VS, 0);
+ END_BATCH();
+
+
/* flush SQ cache */
- cp_set_surface_sync(pScrn, accel_state->ib, SH_ACTION_ENA_bit,
+/* cp_set_surface_sync(pScrn, accel_state->ib, SH_ACTION_ENA_bit,
accel_state->ps_size, accel_state->ps_mc_addr,
- accel_state->shaders_bo, RADEON_GEM_DOMAIN_VRAM, 0);
+ accel_state->shaders_bo, RADEON_GEM_DOMAIN_VRAM, 0); */
+
+ BEGIN_BATCH(7);
+ /* PACK3(accel_state->ib, IT_SURFACE_SYNC, 4); */
+ E32X5((accel_state->ib), RADEON_CP_PACKET3 | ((IT_SURFACE_SYNC) << 8) | ((3 & 0x3fff) << 16),
+ SH_ACTION_ENA_bit,
+ ((512 + 255) >> 8),
+ (accel_state->ps_mc_addr >> 8),
+ 10); /* poll interval */
+ RELOC_BATCH(accel_state->shaders_bo, RADEON_GEM_DOMAIN_VRAM, 0);
+ END_BATCH();
+
ps_conf.shader_addr = accel_state->ps_mc_addr;
ps_conf.num_gprs = 3;
@@ -561,14 +593,14 @@ R600DisplayTexturedVideo(ScrnInfoPtr pScrn, RADEONPortPrivPtr pPriv)
vb[3] = (float)srcY;
vb[4] = (float)dstX;
- vb[5] = (float)(dstY + dsth);
+ vb[5] = vb[9] = (float)(dstY + dsth);
vb[6] = (float)srcX;
- vb[7] = (float)(srcY + srch);
+ vb[7] = vb[11] = (float)(srcY + srch);
vb[8] = (float)(dstX + dstw);
- vb[9] = (float)(dstY + dsth);
+/* vb[9] = (float)(dstY + dsth); */
vb[10] = (float)(srcX + srcw);
- vb[11] = (float)(srcY + srch);
+/* vb[11] = (float)(srcY + srch); */
radeon_vbo_commit(pScrn);
diff --git a/src/r6xx_accel.c b/src/r6xx_accel.c
index d7a95a4..c09c966 100644
--- a/src/r6xx_accel.c
+++ b/src/r6xx_accel.c
@@ -128,8 +128,9 @@ wait_3d_idle_clean(ScrnInfoPtr pScrn, drmBufPtr ib)
//flush caches, don't generate timestamp
BEGIN_BATCH(5);
- PACK3(ib, IT_EVENT_WRITE, 1);
- E32(ib, CACHE_FLUSH_AND_INV_EVENT);
+/* PACK3(ib, IT_EVENT_WRITE, 1); */
+ E32X2(ib, RADEON_CP_PACKET3 | ((IT_EVENT_WRITE) << 8),
+ /* E32(ib, */ CACHE_FLUSH_AND_INV_EVENT);
// wait for 3D idle clean
EREG(ib, WAIT_UNTIL, (WAIT_3D_IDLE_bit |
WAIT_3D_IDLECLEAN_bit));
@@ -153,14 +154,16 @@ start_3d(ScrnInfoPtr pScrn, drmBufPtr ib)
if (info->ChipFamily < CHIP_FAMILY_RV770) {
BEGIN_BATCH(5);
- PACK3(ib, IT_START_3D_CMDBUF, 1);
- E32(ib, 0);
+/* PACK3(ib, IT_START_3D_CMDBUF, 1);*/
+ E32X2(ib, RADEON_CP_PACKET3 | ((IT_START_3D_CMDBUF) << 8),
+ /* E32(ib, */ 0);
} else
BEGIN_BATCH(3);
- PACK3(ib, IT_CONTEXT_CONTROL, 2);
- E32(ib, 0x80000000);
- E32(ib, 0x80000000);
+/* PACK3(ib, IT_CONTEXT_CONTROL, 2); */
+ E32X3(ib, RADEON_CP_PACKET3 | ((IT_CONTEXT_CONTROL) << 8) | (1 << 16),
+ /* E32(ib, */ 0x80000000,
+ /* E32(ib, */ 0x80000000);
END_BATCH();
}
@@ -212,12 +215,12 @@ sq_setup(ScrnInfoPtr pScrn, drmBufPtr ib, sq_config_t *sq_conf)
BEGIN_BATCH(8);
PACK0(ib, SQ_CONFIG, 6);
- E32(ib, sq_config);
- E32(ib, sq_gpr_resource_mgmt_1);
- E32(ib, sq_gpr_resource_mgmt_2);
- E32(ib, sq_thread_resource_mgmt);
- E32(ib, sq_stack_resource_mgmt_1);
- E32(ib, sq_stack_resource_mgmt_2);
+ E32X6(ib, sq_config,
+ /* E32(ib, */ sq_gpr_resource_mgmt_1,
+ /* E32(ib, */ sq_gpr_resource_mgmt_2,
+ /* E32(ib, */ sq_thread_resource_mgmt,
+ /* E32(ib, */ sq_stack_resource_mgmt_1,
+ /* E32(ib, */ sq_stack_resource_mgmt_2);
END_BATCH();
}
@@ -266,30 +269,34 @@ set_render_target(ScrnInfoPtr pScrn, drmBufPtr ib, cb_config_t *cb_conf, uint32_
if ((info->ChipFamily > CHIP_FAMILY_R600) &&
(info->ChipFamily < CHIP_FAMILY_RV770)) {
BEGIN_BATCH(2);
- PACK3(ib, IT_SURFACE_BASE_UPDATE, 1);
- E32(ib, (2 << cb_conf->id));
+/* PACK3(ib, IT_SURFACE_BASE_UPDATE, 1);
+ E32(ib, (2 << cb_conf->id)); */
+ E32X2(ib, RADEON_CP_PACKET3 | ((IT_SURFACE_BASE_UPDATE) << 8),
+ /* E32(ib, */ (2 << cb_conf->id));
END_BATCH();
}
/* Set CMASK & TILE buffer to the offset of color buffer as
* we don't use those this shouldn't cause any issue and we
* then have a valid cmd stream
*/
- BEGIN_BATCH(3 + 2);
- EREG(ib, (CB_COLOR0_TILE + (4 * cb_conf->id)), (0 >> 8)); // CMASK per-tile data base/256
+h = 4 * cb_conf->id;
+ BEGIN_BATCH(22);
+/* BEGIN_BATCH(3 + 2);*/
+ EREG(ib, (CB_COLOR0_TILE + (h)), (0 >> 8)); // CMASK per-tile data base/256
RELOC_BATCH(cb_conf->bo, 0, domain);
- END_BATCH();
- BEGIN_BATCH(3 + 2);
- EREG(ib, (CB_COLOR0_FRAG + (4 * cb_conf->id)), (0 >> 8)); // FMASK per-tile data base/256
+/* END_BATCH();
+ BEGIN_BATCH(3 + 2);*/
+ EREG(ib, (CB_COLOR0_FRAG + (h)), (0 >> 8)); // FMASK per-tile data base/256
RELOC_BATCH(cb_conf->bo, 0, domain);
- END_BATCH();
- BEGIN_BATCH(12);
+/* END_BATCH();
+ BEGIN_BATCH(12); */
// pitch only for ARRAY_LINEAR_GENERAL, other tiling modes require addrlib
- EREG(ib, (CB_COLOR0_SIZE + (4 * cb_conf->id)), ((pitch << PITCH_TILE_MAX_shift) |
+ EREG(ib, (CB_COLOR0_SIZE + (h)), ((pitch << PITCH_TILE_MAX_shift) |
(slice << SLICE_TILE_MAX_shift)));
- EREG(ib, (CB_COLOR0_VIEW + (4 * cb_conf->id)), ((0 << SLICE_START_shift) |
+ EREG(ib, (CB_COLOR0_VIEW + (h)), ((0 << SLICE_START_shift) |
(0 << SLICE_MAX_shift)));
- EREG(ib, (CB_COLOR0_INFO + (4 * cb_conf->id)), cb_color_info);
- EREG(ib, (CB_COLOR0_MASK + (4 * cb_conf->id)), ((0 << CMASK_BLOCK_MAX_shift) |
+ EREG(ib, (CB_COLOR0_INFO + (h)), cb_color_info);
+ EREG(ib, (CB_COLOR0_MASK + (h)), ((0 << CMASK_BLOCK_MAX_shift) |
(0 << FMASK_TILE_MAX_shift)));
END_BATCH();
}
@@ -307,10 +314,10 @@ cp_set_surface_sync(ScrnInfoPtr pScrn, drmBufPtr ib, uint32_t sync_type, uint32_
BEGIN_BATCH(5 + 2);
PACK3(ib, IT_SURFACE_SYNC, 4);
- E32(ib, sync_type);
- E32(ib, cp_coher_size);
- E32(ib, (mc_addr >> 8));
- E32(ib, 10); /* poll interval */
+ E32X4(ib, sync_type,
+ /* E32(ib, */ cp_coher_size,
+ /* E32(ib, */ (mc_addr >> 8),
+ /* E32(ib, */ 10); /* poll interval */
RELOC_BATCH(bo, rdomains, wdomain);
END_BATCH();
}
@@ -364,16 +371,18 @@ void cp_wait_vline_sync(ScrnInfoPtr pScrn, drmBufPtr ib, PixmapPtr pPix,
(stop << AVIVO_D1MODE_VLINE_END_SHIFT));
/* tell the CP to poll the VLINE state register */
- PACK3(ib, IT_WAIT_REG_MEM, 6);
- E32(ib, IT_WAIT_REG | IT_WAIT_EQ);
- E32(ib, IT_WAIT_ADDR(AVIVO_D1MODE_VLINE_STATUS));
- E32(ib, 0);
- E32(ib, 0); // Ref value
- E32(ib, AVIVO_D1MODE_VLINE_STAT); // Mask
- E32(ib, 10); // Wait interval
+/* PACK3(ib, IT_WAIT_REG_MEM, 6); */
+ E32X7(ib, RADEON_CP_PACKET3 | ((IT_WAIT_REG_MEM) << 8) | ( 5 << 16 ),
+ /* E32(ib, */ IT_WAIT_REG | IT_WAIT_EQ ,
+ /* E32(ib, */ IT_WAIT_ADDR(AVIVO_D1MODE_VLINE_STATUS),
+ /* E32(ib, */ 0,
+ /* E32(ib, */ 0, // Ref value
+ /* E32(ib, */ AVIVO_D1MODE_VLINE_STAT, // Mask
+ /* E32(ib, */ 10); // Wait interval
/* add crtc reloc */
- PACK3(ib, IT_NOP, 1);
- E32(ib, drmmode_crtc->mode_crtc->crtc_id);
+/* PACK3(ib, IT_NOP, 1); */
+ E32X2(ib, RADEON_CP_PACKET3 | ((IT_NOP) << 8),
+ /* E32(ib, */ drmmode_crtc->mode_crtc->crtc_id);
END_BATCH();
} else
#endif
@@ -388,12 +397,12 @@ void cp_wait_vline_sync(ScrnInfoPtr pScrn, drmBufPtr ib, PixmapPtr pPix,
/* tell the CP to poll the VLINE state register */
PACK3(ib, IT_WAIT_REG_MEM, 6);
- E32(ib, IT_WAIT_REG | IT_WAIT_EQ);
- E32(ib, IT_WAIT_ADDR(AVIVO_D1MODE_VLINE_STATUS + radeon_crtc->crtc_offset));
- E32(ib, 0);
- E32(ib, 0); // Ref value
- E32(ib, AVIVO_D1MODE_VLINE_STAT); // Mask
- E32(ib, 10); // Wait interval
+ E32X3(ib, IT_WAIT_REG | IT_WAIT_EQ,
+ /* E32(ib, */ IT_WAIT_ADDR(AVIVO_D1MODE_VLINE_STATUS + radeon_crtc->crtc_offset),
+ /* E32(ib, */ 0);
+ E32X3(ib, 0, // Ref value
+ /* E32(ib, */ AVIVO_D1MODE_VLINE_STAT, // Mask
+ /* E32(ib, */ 10); // Wait interval
END_BATCH();
}
}
@@ -410,12 +419,13 @@ fs_setup(ScrnInfoPtr pScrn, drmBufPtr ib, shader_config_t *fs_conf, uint32_t dom
if (fs_conf->dx10_clamp)
sq_pgm_resources |= SQ_PGM_RESOURCES_FS__DX10_CLAMP_bit;
- BEGIN_BATCH(3 + 2);
+ BEGIN_BATCH(11);
+/* BEGIN_BATCH(3 + 2); */
EREG(ib, SQ_PGM_START_FS, fs_conf->shader_addr >> 8);
RELOC_BATCH(fs_conf->bo, domain, 0);
- END_BATCH();
+/* END_BATCH();
- BEGIN_BATCH(6);
+ BEGIN_BATCH(6); */
EREG(ib, SQ_PGM_RESOURCES_FS, sq_pgm_resources);
EREG(ib, SQ_PGM_CF_OFFSET_FS, 0);
END_BATCH();
@@ -437,12 +447,13 @@ vs_setup(ScrnInfoPtr pScrn, drmBufPtr ib, shader_config_t *vs_conf, uint32_t dom
if (vs_conf->uncached_first_inst)
sq_pgm_resources |= UNCACHED_FIRST_INST_bit;
- BEGIN_BATCH(3 + 2);
+ BEGIN_BATCH(9 + 2);
+/* BEGIN_BATCH(3 + 2); */
EREG(ib, SQ_PGM_START_VS, vs_conf->shader_addr >> 8);
RELOC_BATCH(vs_conf->bo, domain, 0);
- END_BATCH();
+/* END_BATCH();
- BEGIN_BATCH(6);
+ BEGIN_BATCH(6); */
EREG(ib, SQ_PGM_RESOURCES_VS, sq_pgm_resources);
EREG(ib, SQ_PGM_CF_OFFSET_VS, 0);
END_BATCH();
@@ -466,12 +477,13 @@ ps_setup(ScrnInfoPtr pScrn, drmBufPtr ib, shader_config_t *ps_conf, uint32_t dom
if (ps_conf->clamp_consts)
sq_pgm_resources |= CLAMP_CONSTS_bit;
- BEGIN_BATCH(3 + 2);
+ BEGIN_BATCH(9 + 5);
+/* BEGIN_BATCH(3 + 2); */
EREG(ib, SQ_PGM_START_PS, ps_conf->shader_addr >> 8);
RELOC_BATCH(ps_conf->bo, domain, 0);
- END_BATCH();
+/* END_BATCH();
- BEGIN_BATCH(9);
+ BEGIN_BATCH(9); */
EREG(ib, SQ_PGM_RESOURCES_PS, sq_pgm_resources);
EREG(ib, SQ_PGM_EXPORTS_PS, ps_conf->export_mode);
EREG(ib, SQ_PGM_CF_OFFSET_PS, 0);
@@ -526,13 +538,13 @@ set_vtx_resource(ScrnInfoPtr pScrn, drmBufPtr ib, vtx_resource_t *res, uint32_t
BEGIN_BATCH(9 + 2);
PACK0(ib, SQ_VTX_RESOURCE + res->id * SQ_VTX_RESOURCE_offset, 7);
- E32(ib, res->vb_addr & 0xffffffff); // 0: BASE_ADDRESS
- E32(ib, (res->vtx_num_entries << 2) - 1); // 1: SIZE
- E32(ib, sq_vtx_constant_word2); // 2: BASE_HI, STRIDE, CLAMP, FORMAT, ENDIAN
- E32(ib, res->mem_req_size << MEM_REQUEST_SIZE_shift); // 3: MEM_REQUEST_SIZE ?!?
- E32(ib, 0); // 4: n/a
- E32(ib, 0); // 5: n/a
- E32(ib, SQ_TEX_VTX_VALID_BUFFER << SQ_VTX_CONSTANT_WORD6_0__TYPE_shift); // 6: TYPE
+ E32X7(ib, res->vb_addr & 0xffffffff, // 0: BASE_ADDRESS
+ /* E32(ib,*/ (res->vtx_num_entries << 2) - 1, // 1: SIZE
+ /* E32(ib,*/ sq_vtx_constant_word2, // 2: BASE_HI, STRIDE, CLAMP, FORMAT, ENDIAN
+ /* E32(ib, */ res->mem_req_size << MEM_REQUEST_SIZE_shift, // 3: MEM_REQUEST_SIZE ?!?
+ /* E32(ib, */ 0, // 4: n/a
+ /* E32(ib, */ 0, // 5: n/a
+ /* E32(ib, */ SQ_TEX_VTX_VALID_BUFFER << SQ_VTX_CONSTANT_WORD6_0__TYPE_shift); // 6: TYPE
RELOC_BATCH(res->bo, domain, 0);
END_BATCH();
}
@@ -592,13 +604,13 @@ set_tex_resource(ScrnInfoPtr pScrn, drmBufPtr ib, tex_resource_t *tex_res, uint3
BEGIN_BATCH(9 + 4);
PACK0(ib, SQ_TEX_RESOURCE + tex_res->id * SQ_TEX_RESOURCE_offset, 7);
- E32(ib, sq_tex_resource_word0);
- E32(ib, sq_tex_resource_word1);
- E32(ib, ((tex_res->base) >> 8));
- E32(ib, ((tex_res->mip_base) >> 8));
- E32(ib, sq_tex_resource_word4);
- E32(ib, sq_tex_resource_word5);
- E32(ib, sq_tex_resource_word6);
+ E32X7(ib, sq_tex_resource_word0,
+ /* E32(ib, */ sq_tex_resource_word1,
+ /* E32(ib, */ ((tex_res->base) >> 8),
+ /* E32(ib, */ ((tex_res->mip_base) >> 8),
+ /* E32(ib, */ sq_tex_resource_word4,
+ /* E32(ib, */ sq_tex_resource_word5,
+ /* E32(ib, */ sq_tex_resource_word6);
RELOC_BATCH(tex_res->bo, domain, 0);
RELOC_BATCH(tex_res->mip_bo, domain, 0);
END_BATCH();
@@ -649,9 +661,9 @@ set_tex_sampler (ScrnInfoPtr pScrn, drmBufPtr ib, tex_sampler_t *s)
BEGIN_BATCH(5);
PACK0(ib, SQ_TEX_SAMPLER_WORD + s->id * SQ_TEX_SAMPLER_WORD_offset, 3);
- E32(ib, sq_tex_sampler_word0);
- E32(ib, sq_tex_sampler_word1);
- E32(ib, sq_tex_sampler_word2);
+ E32X3(ib, sq_tex_sampler_word0,
+ /* E32(ib, */ sq_tex_sampler_word1,
+ /* E32(ib, */ sq_tex_sampler_word2);
END_BATCH();
}
@@ -910,14 +922,14 @@ set_default_state(ScrnInfoPtr pScrn, drmBufPtr ib)
EREG(ib, SQ_VTX_START_INST_LOC, 0);
PACK0(ib, SQ_ESGS_RING_ITEMSIZE, 9);
- E32(ib, 0); // SQ_ESGS_RING_ITEMSIZE
- E32(ib, 0); // SQ_GSVS_RING_ITEMSIZE
- E32(ib, 0); // SQ_ESTMP_RING_ITEMSIZE
- E32(ib, 0); // SQ_GSTMP_RING_ITEMSIZE
- E32(ib, 0); // SQ_VSTMP_RING_ITEMSIZE
- E32(ib, 0); // SQ_PSTMP_RING_ITEMSIZE
- E32(ib, 0); // SQ_FBUF_RING_ITEMSIZE
- E32(ib, 0); // SQ_REDUC_RING_ITEMSIZE
+ E32X4(ib, 0, // SQ_ESGS_RING_ITEMSIZE
+ /* E32(ib, */ 0, // SQ_GSVS_RING_ITEMSIZE
+ /* E32(ib, */ 0, // SQ_ESTMP_RING_ITEMSIZE
+ /* E32(ib, */ 0); // SQ_GSTMP_RING_ITEMSIZE
+ E32X4(ib, 0, // SQ_VSTMP_RING_ITEMSIZE
+ /* E32(ib, */ 0, // SQ_PSTMP_RING_ITEMSIZE
+ /* E32(ib, */ 0, // SQ_FBUF_RING_ITEMSIZE
+ /* E32(ib, */ 0); // SQ_REDUC_RING_ITEMSIZE
E32(ib, 0); // SQ_GS_VERT_ITEMSIZE
// DB
@@ -948,18 +960,18 @@ set_default_state(ScrnInfoPtr pScrn, drmBufPtr ib)
// CB
PACK0(ib, CB_BLEND_RED, 4);
- E32(ib, 0x00000000);
- E32(ib, 0x00000000);
- E32(ib, 0x00000000);
- E32(ib, 0x00000000);
+ E32X4(ib, 0x00000000,
+ /* E32(ib, */ 0x00000000,
+ /* E32(ib, */ 0x00000000,
+ /* E32(ib, */ 0x00000000);
END_BATCH();
if (info->ChipFamily < CHIP_FAMILY_RV770) {
BEGIN_BATCH(11);
PACK0(ib, CB_FOG_RED, 3);
- E32(ib, 0x00000000);
- E32(ib, 0x00000000);
- E32(ib, 0x00000000);
+ E32X3(ib, 0x00000000,
+ /* E32(ib, */ 0x00000000,
+ /* E32(ib, */ 0x00000000);
PACK0(ib, CB_CLEAR_RED, 4);
EFLOAT(ib, 1.0); /* WTF? */
EFLOAT(ib, 0.0);
@@ -970,10 +982,10 @@ set_default_state(ScrnInfoPtr pScrn, drmBufPtr ib)
BEGIN_BATCH(18);
PACK0(ib, CB_CLRCMP_CONTROL, 4);
- E32(ib, 1 << CLRCMP_FCN_SEL_shift); // CB_CLRCMP_CONTROL: use CLRCMP_FCN_SRC
- E32(ib, 0); // CB_CLRCMP_SRC
- E32(ib, 0); // CB_CLRCMP_DST
- E32(ib, 0); // CB_CLRCMP_MSK
+ E32X4(ib, 1 << CLRCMP_FCN_SEL_shift, // CB_CLRCMP_CONTROL: use CLRCMP_FCN_SRC
+ /* E32(ib, */ 0, // CB_CLRCMP_SRC
+ /* E32(ib, */ 0, // CB_CLRCMP_DST
+ /* E32(ib, */ 0); // CB_CLRCMP_MSK
EREG(ib, CB_SHADER_MASK, (0xf << OUTPUT0_ENABLE_shift));
EREG(ib, R7xx_CB_SHADER_CONTROL, (RT0_ENABLE_bit));
@@ -1137,14 +1149,16 @@ draw_immd(ScrnInfoPtr pScrn, drmBufPtr ib, draw_config_t *draw_conf, uint32_t *i
BEGIN_BATCH(8 + count);
EREG(ib, VGT_PRIMITIVE_TYPE, draw_conf->prim_type);
- PACK3(ib, IT_INDEX_TYPE, 1);
- E32(ib, draw_conf->index_type);
- PACK3(ib, IT_NUM_INSTANCES, 1);
- E32(ib, draw_conf->num_instances);
+/* PACK3(ib, IT_INDEX_TYPE, 1); */
+ E32X4(ib, RADEON_CP_PACKET3 | ((IT_INDEX_TYPE) << 8),
+ /* E32(ib, */ draw_conf->index_type ,
+/* PACK3(ib, IT_NUM_INSTANCES, 1); */
+ /* E32(ib, */ RADEON_CP_PACKET3 | ((IT_NUM_INSTANCES) << 8),
+ /* E32(ib, */ draw_conf->num_instances);
PACK3(ib, IT_DRAW_INDEX_IMMD, count);
- E32(ib, draw_conf->num_indices);
- E32(ib, draw_conf->vgt_draw_initiator);
+ E32X2(ib, draw_conf->num_indices,
+ draw_conf->vgt_draw_initiator);
if (draw_conf->index_type == DI_INDEX_SIZE_16_BIT) {
for (i = 0; i < draw_conf->num_indices; i += 2) {
@@ -1167,13 +1181,16 @@ draw_auto(ScrnInfoPtr pScrn, drmBufPtr ib, draw_config_t *draw_conf)
BEGIN_BATCH(10);
EREG(ib, VGT_PRIMITIVE_TYPE, draw_conf->prim_type);
- PACK3(ib, IT_INDEX_TYPE, 1);
- E32(ib, draw_conf->index_type);
- PACK3(ib, IT_NUM_INSTANCES, 1);
- E32(ib, draw_conf->num_instances);
- PACK3(ib, IT_DRAW_INDEX_AUTO, 2);
- E32(ib, draw_conf->num_indices);
- E32(ib, draw_conf->vgt_draw_initiator);
+/* PACK3(ib, IT_INDEX_TYPE, 1); */
+ E32X7(ib, RADEON_CP_PACKET3 | ((IT_INDEX_TYPE) << 8),
+ /* E32(ib, */ draw_conf->index_type,
+ /* PACK3(ib, IT_NUM_INSTANCES, 1); */
+ /* E32(ib, */ RADEON_CP_PACKET3 | ((IT_NUM_INSTANCES) << 8),
+ /* E32(ib, */ draw_conf->num_instances,
+/* PACK3(ib, IT_DRAW_INDEX_AUTO, 2); */
+ /* E32(ib, */ RADEON_CP_PACKET3 | ((IT_DRAW_INDEX_AUTO) << 8) | (1 << 16),
+ /* E32(ib, */ draw_conf->num_indices,
+ /* E32(ib, */ draw_conf->vgt_draw_initiator);
END_BATCH();
}
@@ -1238,8 +1255,8 @@ void r600_finish_op(ScrnInfoPtr pScrn, int vtx_size)
if (accel_state->vb_start_op == -1)
return;
- CLEAR (draw_conf);
- CLEAR (vtx_res);
+/* CLEAR (draw_conf); */
+/* CLEAR (vtx_res); */
if (accel_state->vb_offset == accel_state->vb_start_op) {
R600IBDiscard(pScrn, accel_state->ib);
@@ -1268,6 +1285,12 @@ void r600_finish_op(ScrnInfoPtr pScrn, int vtx_size)
vtx_res.id = SQ_VTX_RESOURCE_vs;
vtx_res.vtx_size_dw = vtx_size / 4;
vtx_res.vtx_num_entries = accel_state->vb_size / 4;
+ vtx_res.clamp_x = 0;
+ vtx_res.format = 0;
+ vtx_res.num_format_all = 0;
+ vtx_res.format_comp_all = 0;
+ vtx_res.srf_mode_all = 0;
+ vtx_res.endian = 0;
vtx_res.mem_req_size = 1;
vtx_res.vb_addr = accel_state->vb_mc_addr + accel_state->vb_start_op;
vtx_res.bo = accel_state->vb_bo;
diff --git a/src/radeon_dummy_bufmgr.h b/src/radeon_dummy_bufmgr.h
index e08e656..4446899 100644
--- a/src/radeon_dummy_bufmgr.h
+++ b/src/radeon_dummy_bufmgr.h
@@ -20,10 +20,54 @@ static inline int radeon_cs_end(Bool dummy, const char *file,
return 0;
}
-static inline void radeon_cs_write_dword(Bool cs, uint32_t dword)
+static inline void radeon_cs_write_two_dwords(Bool cs, uint32_t dword1,
+ uint32_t dword2)
{
}
+static inline void radeon_cs_write_three_dwords(Bool cs, uint32_t dword1,
+ uint32_t dword2,
+ uint32_t dword3)
+{
+}
+
+static inline void radeon_cs_write_four_dwords(Bool cs, uint32_t dword1,
+ uint32_t dword2,
+ uint32_t dword3,
+ uint32_t dword4)
+{
+}
+
+static inline void radeon_cs_write_five_dwords(Bool cs, uint32_t dword1,
+ uint32_t dword2,
+ uint32_t dword3,
+ uint32_t dword4,
+ uint32_t dword5)
+{
+}
+
+static inline void radeon_cs_write_six_dwords(Bool cs, uint32_t dword1,
+ uint32_t dword2,
+ uint32_t dword3,
+ uint32_t dword4,
+ uint32_t dword5,
+ uint32_t dword6)
+{
+}
+
+static inline void radeon_cs_write_seven_dwords(Bool cs, uint32_t dword1,
+ uint32_t dword2,
+ uint32_t dword3,
+ uint32_t dword4,
+ uint32_t dword5,
+ uint32_t dword6,
+ uint32_t dword7)
+{
+}
+
+
+radeon_cs_write_seven_dwords(info->cs, (dword1), (dword2),(dword3),(dword4), (dword5), (dword6), (dword7));
+
static inline int radeon_cs_write_reloc(Bool cs,
struct radeon_bo *bo,
uint32_t read_domain,