rendered paste body/* * Carsten Langgaard, carstenl@mips.com * Copyright (C) 2002 MIPS Technologies, Inc. All rights reserved. * Copyright (C) 2003 Ralf Baechle (ralf@linux-mips.org) * * This program is free software; you can distribute it and/or modify it * under the terms of the GNU General Public License (Version 2) as * published by the Free Software Foundation. * * This program is distributed in the hope it will be useful, but WITHOUT * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License * for more details. * * You should have received a copy of the GNU General Public License along * with this program; if not, write to the Free Software Foundation, Inc., * 59 Temple Place - Suite 330, Boston MA 02111-1307, USA. * * Routines for generic manipulation of the interrupts found on the MIPS * Sead board. */#include <linux/init.h>#include <linux/irq.h>#include <asm/irq.h>#include <linux/interrupt.h>#include <linux/kernel_stat.h>#include <linux/module.h>#include <asm/mips-boards/ohio.h>#include <asm/mips-boards/ohioint.h>#include <asm/mach_avm.h>#if defined(CONFIG_VLYNQ_SUPPORT)#include <asm/mips-boards/ohio_vlynq.h>#endif /*--- #if defined(CONFIG_VLYNQ_SUPPORT) ---*/#include <asm/mach-ohio/hw_irq.h>static void __init ohio_init_irq(void);/*------------------------------------------------------------------------------------------*\\*------------------------------------------------------------------------------------------*/static void ohio_hw0_irqdispatch(struct pt_regs *regs) { /* TODO */ struct _irq_hw *IRQ = (struct _irq_hw *)OHIO_IRQ_CTRL_BASE; unsigned int priority_index_reg = IRQ->priority_index_reg; unsigned int irq = (priority_index_reg >> 16) & 0x3F; extern void r4k_wait_end(void); r4k_wait_end(); irq += MIPS_EXCEPTION_OFFSET; /*--- printk("[ohio_hw0_irqdispatch] irq=%u chan_nr=%u\n", irq, chan_nr); ---*/ if(irq == MIPS_EXCEPTION_OFFSET) { unsigned int _irq; for(_irq = 0 ; _irq < 32 ; _irq++) { if(IRQ->exception_clear_status_reg & (1 << _irq)) break; } if(_irq != 32) do_IRQ(_irq, regs); }#if defined(CONFIG_VLYNQ_SUPPORT) else if(irq == OHIOINT_VLYNQ0) { unsigned int vlynq_irq = vlynq_get_irq(0) + OHIO_INT_START_VIRTUAL; if(vlynq_irq != (unsigned int)-1) do_IRQ(vlynq_irq, regs); }#endif /*--- #if defined(CONFIG_VLYNQ_SUPPORT) ---*/ kstat_this_cpu.irqs[MIPS_EXCEPTION_OFFSET - 2]++; do_IRQ(irq, regs);}/*------------------------------------------------------------------------------------------*\\*------------------------------------------------------------------------------------------*/static void ohio_hw1_irqdispatch(struct pt_regs *regs) /* TODO */{ /*--- do_IRQ(OHIOINT_UART1, regs); ---*/ /*--- struct irq_desc *desc; ---*/ /*--- int cpu = smp_processor_id(); ---*/ struct _irq_hw *IRQ = (struct _irq_hw *)OHIO_IRQ_CTRL_BASE; unsigned int priority_index_reg = IRQ->priority_index_reg; unsigned int irq = (priority_index_reg >> 16) & 0x3F; unsigned int chan_nr = priority_index_reg & 0x3F; printk("[ohio_hw1_irqdispatch] irq=%u chan_nr=%u\n", irq, chan_nr);}static inline int clz(unsigned long x){ __asm__ ( " .set push \n" " .set mips32 \n" " clz %0, %1 \n" " .set pop \n" : "=r" (x) : "r" (x)); return x;}/* * Version of ffs that only looks at bits 12..15. */static inline unsigned int irq_ffs(unsigned int pending){#if defined(CONFIG_CPU_MIPS32) || defined(CONFIG_CPU_MIPS64) return -clz(pending) + 31 - CAUSEB_IP;#else unsigned int a0 = 7; unsigned int t0; t0 = s0 & 0xf000; t0 = t0 < 1; t0 = t0 << 2; a0 = a0 - t0; s0 = s0 << t0; t0 = s0 & 0xc000; t0 = t0 < 1; t0 = t0 << 1; a0 = a0 - t0; s0 = s0 << t0; t0 = s0 & 0x8000; t0 = t0 < 1; //t0 = t0 << 2; a0 = a0 - t0; //s0 = s0 << t0; return a0;#endif/* TODO * IRQs on the AR7 board works. I don't know _how_ works, so i written * random statements hoping that works. This wont unlikely work * * MIPS IRQ Source * -------- ------ * 0 Dunno * 1 Dunno * 2 Dunno * 3 Dunno * 4 Dunno * 5 Dunno * 6 Dunno * 7 Dunno * * We handle the IRQ according to _our_ priority which is: * * Alphabetical order * * then we just return, hoping that magic smoke * won't be released from the board */asmlinkage void plat_irq_dispatch(struct pt_regs *regs){ unsigned int pending = read_c0_cause() & read_c0_status() & ST0_IM; int irq; irq = irq_ffs(pending); if (irq > 0) do_IRQ(MIPSCPU_INT_BASE + irq, regs); else spurious_interrupt(regs);}/*------------------------------------------------------------------------------------------*\\*------------------------------------------------------------------------------------------*/static struct _ohio_nsec_timer { unsigned long long offset; unsigned int last; unsigned long clock_faktor;} nT = { 0ULL, 0U, 0UL };/*------------------------------------------------------------------------------------------*\\*------------------------------------------------------------------------------------------*/unsigned long long ohio_nsec_timer(void) { unsigned int count; if(nT.clock_faktor == 0) { /*--- wie viele n-sec pro clock ---*/ nT.clock_faktor = (unsigned long)(1000000000 / (ohio_get_clock(avm_clock_id_cpu) / 2)); } local_irq_disable(); count = read_c0_count() * nT.clock_faktor; if(count < nT.last) nT.offset += 0xFFFFFFFF * nT.clock_faktor; nT.last = count; local_irq_enable(); return (unsigned long long)count + nT.offset;}/*------------------------------------------------------------------------------------------*\\*------------------------------------------------------------------------------------------*/void ohio_timer_interrupt(void) { unsigned int count; count = read_c0_count(); if(count < nT.last) { nT.offset += ((unsigned long long)1 << 32); nT.offset = count; } return;}/*------------------------------------------------------------------------------------------*\\*------------------------------------------------------------------------------------------*/extern void mips_cpu_irq_init(int irq_base);void __init arch_init_irq(void) /* TODO */{ ohio_init_irq(); /* * Mask out all interrupt */ clear_c0_status(0x0000ff00); mips_cpu_irq_init(0);}/*------------------------------------------------------------------------------------------*\\*------------------------------------------------------------------------------------------*/irqreturn_t dummy_timer_irq(int irq, void *context, struct pt_regs *regs) { panic("dummy_timer_irq must not be called\n"); return 0;}/*------------------------------------------------------------------------------------------*\\*------------------------------------------------------------------------------------------*/irqreturn_t dummy_system_irq_2(int irq, void *context, struct pt_regs *regs) { panic("dummy_system_irq_2 must not be called\n"); return 0;}/*------------------------------------------------------------------------------------------*\\*------------------------------------------------------------------------------------------*/static int __init ohio_install_dummy_irq_functions(void) { request_irq(MIPS_EXCEPTION_OFFSET - 7, dummy_timer_irq, 0, "system timer", NULL); request_irq(MIPS_EXCEPTION_OFFSET - 2, dummy_system_irq_2, 0, "OHIO primary", NULL); return 0;}/*late_initcall(ohio_install_dummy_irq_functions);*//*------------------------------------------------------------------------------------------*\\*------------------------------------------------------------------------------------------*/static void __init ohio_init_irq(void) { struct _irq_hw *IRQ = (struct _irq_hw *)OHIO_IRQ_CTRL_BASE;/* struct _hw_clock *CLOCK = (struct _hw_clock *)OHIO_CLOCK_BASE;*/ unsigned int irq; IRQ->enable_clear_reg[0] = 0xFFFFFFFF; IRQ->enable_clear_reg[1] = 0xFFFFFFFF; IRQ->status_clear_reg[0] = 0xFFFFFFFF; IRQ->status_clear_reg[1] = 0xFFFFFFFF; /*--- IRQ->enable_set_reg[0] = ---*/ /*--- IRQ->enable_set_reg[1] = ---*/ /*--- IRQ->polarity_reg[0] = ---*/ /*--- IRQ->polarity_reg[1] = ---*/ /*--- IRQ->type_reg[0] = ---*/ /*--- IRQ->type_reg[1] = ---*/ /*--- IRQ->exception_set_status_reg = ---*/ IRQ->exception_enable_clear_reg = 0xFFFFFFFF; IRQ->exception_clear_status_reg = 0xFFFFFFFF; /*--- IRQ->exception_enable_set_reg = ---*/ /*--- IRQ->pacing_prescale_reg = ---*/ /*--- IRQ->pacing_map_reg = ---*/ /*--- IRQ->pacing_max_reg = ---*/ IRQ->polarity_reg[0] = 0; IRQ->polarity_reg[1] = 0; IRQ->type_reg[0] = 0 | (1 << 7) | (1 << 8) | (1 << 22) | (1 << 23) | (1 << 24) | (1 << 28) | (1 << 29) ; IRQ->type_reg[1] = 0x00000000; for(irq = 0 ; irq < sizeof(IRQ->channel_number_reg) / sizeof(IRQ->channel_number_reg[0]) ; irq++) { IRQ->channel_number_reg[irq] = irq; } /*--- printk("[ohio_init_irq] ebase = 0x%x\n", read_c0_ebase()); ---*/}/*EXPORT_SYMBOL (ohio_nsec_timer);*/