rendered paste bodydiff --git a/hw/device-assignment.c b/hw/device-assignment.cindex 4522ef4..c8db108 100644--- a/hw/device-assignment.c+++ b/hw/device-assignment.c@@ -46,7 +46,7 @@ #define IORESOURCE_DMA 0x00000800 #define IORESOURCE_PREFETCH 0x00001000 /* No side effects */ -/* #define DEVICE_ASSIGNMENT_DEBUG 1 */+#define DEVICE_ASSIGNMENT_DEBUG 1 #ifdef DEVICE_ASSIGNMENT_DEBUG #define DEBUG(fmt, ...) \@@ -155,7 +155,9 @@ static uint32_t slow_bar_readb(void *opaque, target_phys_addr_t addr) uint32_t r; r = *in;- DEBUG("slow_bar_readl addr=0x" TARGET_FMT_plx " val=0x%08x\n", addr, r);++ DEBUG("pbase=%08" FMT_PCIBUS ",vbase=%p,addr=0x" TARGET_FMT_plx ",val=0x%02x\n",+ d->e_physbase,d->u.r_virtbase,addr, r); return r; }@@ -167,7 +169,8 @@ static uint32_t slow_bar_readw(void *opaque, target_phys_addr_t addr) uint32_t r; r = *in;- DEBUG("slow_bar_readl addr=0x" TARGET_FMT_plx " val=0x%08x\n", addr, r);+ DEBUG("pbase=%08" FMT_PCIBUS ",vbase=%p,addr=0x" TARGET_FMT_plx ",val=0x%04x\n", + d->e_physbase,d->u.r_virtbase,addr, r); return r; }@@ -179,7 +182,8 @@ static uint32_t slow_bar_readl(void *opaque, target_phys_addr_t addr) uint32_t r; r = *in;- DEBUG("slow_bar_readl addr=0x" TARGET_FMT_plx " val=0x%08x\n", addr, r);+ DEBUG("pbase=%08" FMT_PCIBUS ",vbase=%p,addr=0x" TARGET_FMT_plx ",val=0x%08x\n", + d->e_physbase, d->u.r_virtbase, addr, r); return r; }@@ -189,7 +193,8 @@ static void slow_bar_writeb(void *opaque, target_phys_addr_t addr, uint32_t val) AssignedDevRegion *d = opaque; uint8_t *out = d->u.r_virtbase + addr; - DEBUG("slow_bar_writeb addr=0x" TARGET_FMT_plx " val=0x%02x\n", addr, val);+ DEBUG("pbase=%08" FMT_PCIBUS ",vbase=%p,addr=0x" TARGET_FMT_plx ",val=0x%02x\n", + d->e_physbase, d->u.r_virtbase, addr, val); *out = val; } @@ -198,7 +203,8 @@ static void slow_bar_writew(void *opaque, target_phys_addr_t addr, uint32_t val) AssignedDevRegion *d = opaque; uint16_t *out = d->u.r_virtbase + addr; - DEBUG("slow_bar_writew addr=0x" TARGET_FMT_plx " val=0x%04x\n", addr, val);+ DEBUG("pbase=%08" FMT_PCIBUS ",vbase=%p,addr=0x" TARGET_FMT_plx ",val=0x%04x\n", + d->e_physbase, d->u.r_virtbase, addr, val); *out = val; } @@ -207,16 +213,41 @@ static void slow_bar_writel(void *opaque, target_phys_addr_t addr, uint32_t val) AssignedDevRegion *d = opaque; uint32_t *out = d->u.r_virtbase + addr; - DEBUG("slow_bar_writel addr=0x" TARGET_FMT_plx " val=0x%08x\n", addr, val);+ DEBUG("pbase=%08" FMT_PCIBUS ",vbase=%p,addr=0x" TARGET_FMT_plx ",val=0x%08x\n", + d->e_physbase, d->u.r_virtbase, addr, val); *out = val; } +static void slow_rom_writeb(void *opaque, target_phys_addr_t addr, uint32_t val)+{+ DEBUG(" addr=0x" TARGET_FMT_plx " val=0x%02x\n", addr, val);++}++static void slow_rom_writew(void *opaque, target_phys_addr_t addr, uint32_t val)+{+ DEBUG(" addr=0x" TARGET_FMT_plx " val=0x%04x\n", addr, val);++}++static void slow_rom_writel(void *opaque, target_phys_addr_t addr, uint32_t val)+{+ DEBUG(" addr=0x" TARGET_FMT_plx " val=0x%08x\n", addr, val);++}+ static CPUWriteMemoryFunc * const slow_bar_write[] = { &slow_bar_writeb, &slow_bar_writew, &slow_bar_writel }; +static CPUWriteMemoryFunc * const slow_rom_write[] = {+ &slow_rom_writeb,+ &slow_rom_writew,+ &slow_rom_writel+};+ static CPUReadMemoryFunc * const slow_bar_read[] = { &slow_bar_readb, &slow_bar_readw,@@ -234,7 +265,7 @@ static void assigned_dev_iomem_map_slow(PCIDevice *pci_dev, int region_num, DEBUG("%s", "slow map\n"); if (region_num == PCI_ROM_SLOT)- m = cpu_register_io_memory(slow_bar_read, NULL, region);+ m = cpu_register_io_memory(slow_bar_read, slow_rom_write, region); else m = cpu_register_io_memory(slow_bar_read, slow_bar_write, region); cpu_register_physical_memory(e_phys, e_size, m);@@ -382,9 +413,9 @@ static void assigned_dev_pci_write_config(PCIDevice *d, uint32_t address, ssize_t ret; AssignedDevice *pci_dev = container_of(d, AssignedDevice, dev); - DEBUG("(%x.%x): address=%04x val=0x%08x len=%d\n",+ DEBUG("(%x.%x): address=%04x val=0x%0*x len=%d\n", ((d->devfn >> 3) & 0x1F), (d->devfn & 0x7),- (uint16_t) address, val, len);+ (uint16_t) address, len*2,val, len); if (address == 0x4) { pci_default_write_config(d, address, val, len);@@ -431,8 +462,8 @@ static uint32_t assigned_dev_pci_read_config(PCIDevice *d, uint32_t address, address == 0x34 || address == 0x3c || address == 0x3d || pci_access_cap_config(d, address, len)) { val = pci_default_read_config(d, address, len);- DEBUG("(%x.%x): address=%04x val=0x%08x len=%d\n",- (d->devfn >> 3) & 0x1F, (d->devfn & 0x7), address, val, len);+ DEBUG("(%x.%x): address=%04x val=0x%0*x len=%d\n",+ (d->devfn >> 3) & 0x1F, (d->devfn & 0x7), address, len*2, val, len); return val; } @@ -455,8 +486,8 @@ again: } do_log:- DEBUG("(%x.%x): address=%04x val=0x%08x len=%d\n",- (d->devfn >> 3) & 0x1F, (d->devfn & 0x7), address, val, len);+ DEBUG("(%x.%x): address=%04x val=0x%0*x len=%d\n",+ (d->devfn >> 3) & 0x1F, (d->devfn & 0x7), address, len*2, val, len); if (!pci_dev->cap.available) { /* kill the special capabilities */@@ -483,7 +514,7 @@ static int assigned_dev_register_regions(PCIRegion *io_regions, /* handle memory io regions */ if (cur_region->type & IORESOURCE_MEM) {- int slow_map = 0;+ int slow_map = 1; int t = cur_region->type & IORESOURCE_PREFETCH ? PCI_BASE_ADDRESS_MEM_PREFETCH : PCI_BASE_ADDRESS_SPACE_MEMORY;