:(

module top(address, data, r_w, clock);

output [15:0] address;
inout [7:0] data;
output r_w;
input clock;
reg [15:0] address;
reg r_w;
wire clock;
wire [7:0] data;

reg [7:0] A,X,Y; // Accumulator, X, Y
reg [7:0] S,P; // Stack pointer, Processor flags
reg [15:0] PC; // Program Counter

reg [7:0] temp_opcode;
reg [7:0] temp_data;
reg [15:0] temp_address;
reg [5:0] temp_state;

always @(posedge clock)
begin
	case(temp_state)
		8'h00 :
			$display("state 0");
		8'h01 :
			$display("state 1");
		8'h02 :
			$display("state 2");
		8'h03 :
			begin
			$display("state 3");
			temp_state <= 8'h00;
			end
	endcase
end

endmodule