The testbench

// Verilog Test Fixture Template

 `timescale 1 ns / 1 ps

module TEST_6502();
	reg test_clock;

	top mytest6502(
		.clock(test_clock)
	);
	
	initial
	begin
		test_clock = 1'b0;
		#10 $finish;
	end
	always
		begin
		#1 test_clock = ~test_clock;
		end


/*
   // The following code initializes the Global Set Reset (GSR) and Global Three-State (GTS) nets
   // Refer to the Synthesis and Simulation Design Guide for more information on this process
   reg GSR;
   assign glbl.GSR = GSR;
   reg GTS;
   assign glbl.GTS = GTS;

   initial begin
      GSR = 1;
      GTS = 0; // GTS is not activated by default
      #100; // GSR is set for 100 ns
      GSR = 0;
   end

  // Initialize Inputs
      `ifdef auto_init

          initial begin
          end

      `endif
*/
endmodule