sim_tb.v

`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company: 
// Engineer: 
// 
// Create Date:    20:39:35 09/03/2006 
// Design Name: 
// Module Name:    top 
// Project Name: 
// Target Devices: 
// Tool versions: 
// Description: 
//
// Dependencies: 
//
// Revision: 
// Revision 0.01 - File Created
// Additional Comments: 
//
//////////////////////////////////////////////////////////////////////////////////
module top(address, data, r_w, clock);

output [15:0] address;
inout [7:0] data;
output r_w;
input clock;
reg [15:0] address;
reg r_w;
wire clock;
wire [7:0] data;

reg [7:0] A,X,Y; // Accumulator, X, Y
reg [7:0] S,P; // Stack pointer, Processor flags
reg [15:0] PC; // Program Counter

reg [7:0] temp_opcode;
reg [7:0] temp_data;
reg [15:0] temp_address;

always
begin
	@(posedge clock) // machine cycle one
		// put PC into address
		$display("loading address into PC...");
		@(posedge clock)
		// read data and do stuff
		$display("reading data from memory...");
		@(posedge clock)
		// increment PC
		$display("incrementing PC...");
		@(posedge clock)
		// burn time (and power)
		$display("burning time...");
	@(posedge clock) // machine cycle two (I hope there aren't any one-cycle instructions)
		// We need a big case statement here - do stuff
		$display("stuff...");
		@(posedge clock)
		// do more stuff
		$display("stuff...");
		@(posedge clock)
		// increment PC, like always
		$display("incrementing PC...");
		@(posedge clock)
		// why do we have this extra clock, anyways?
		$display("burning time...");
end

endmodule