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diff --git a/src/mesa/drivers/dri/r600/r700_assembler.c b/src/mesa/drivers/dri/r600/r700_assembler.cindex 2d8480d..d4198bf 100644--- a/src/mesa/drivers/dri/r600/r700_assembler.c+++ b/src/mesa/drivers/dri/r600/r700_assembler.c@@ -1152,36 +1152,45 @@ GLboolean tex_src(r700_AssemblerBase *pAsm)       GLboolean bValidTexCoord = GL_FALSE; -    switch (pILInst->SrcReg[0].File)+    if(pAsm->aArgSubst[1] >= 0)     {-    case PROGRAM_TEMPORARY:-        bValidTexCoord = GL_TRUE;--        pAsm->S[0].src.reg   = pILInst->SrcReg[0].Index + pAsm->starting_temp_register_number;+        setaddrmode_PVSSRC(&(pAsm->S[0].src), ADDR_ABSOLUTE);         pAsm->S[0].src.rtype = SRC_REG_TEMPORARY;--        break;-    case PROGRAM_INPUT:-        switch (pILInst->SrcReg[0].Index)+        pAsm->S[0].src.reg   = pAsm->aArgSubst[1];+	bValidTexCoord = GL_TRUE;+    }+    else +    {+        switch (pILInst->SrcReg[0].File)         {-        case FRAG_ATTRIB_COL0:-        case FRAG_ATTRIB_COL1:-        case FRAG_ATTRIB_TEX0:-        case FRAG_ATTRIB_TEX1:-        case FRAG_ATTRIB_TEX2:-        case FRAG_ATTRIB_TEX3:-        case FRAG_ATTRIB_TEX4:-        case FRAG_ATTRIB_TEX5:-        case FRAG_ATTRIB_TEX6:-        case FRAG_ATTRIB_TEX7:+        case PROGRAM_TEMPORARY:             bValidTexCoord = GL_TRUE; -            pAsm->S[0].src.reg   = pAsm->uiFP_AttributeMap[pILInst->SrcReg[0].Index];-            pAsm->S[0].src.rtype = SRC_REG_INPUT;+            pAsm->S[0].src.reg   = pILInst->SrcReg[0].Index + pAsm->starting_temp_register_number;+            pAsm->S[0].src.rtype = SRC_REG_TEMPORARY;++            break;+        case PROGRAM_INPUT:+            switch (pILInst->SrcReg[0].Index)+            {+            case FRAG_ATTRIB_COL0:+            case FRAG_ATTRIB_COL1:+            case FRAG_ATTRIB_TEX0:+            case FRAG_ATTRIB_TEX1:+            case FRAG_ATTRIB_TEX2:+            case FRAG_ATTRIB_TEX3:+            case FRAG_ATTRIB_TEX4:+            case FRAG_ATTRIB_TEX5:+            case FRAG_ATTRIB_TEX6:+            case FRAG_ATTRIB_TEX7:+                bValidTexCoord = GL_TRUE;+ +                pAsm->S[0].src.reg   = pAsm->uiFP_AttributeMap[pILInst->SrcReg[0].Index];+                pAsm->S[0].src.rtype = SRC_REG_INPUT;+            }+            break;         }-        break;     }-     if(GL_TRUE == bValidTexCoord)     {          setaddrmode_PVSSRC(&(pAsm->S[0].src), ADDR_ABSOLUTE);@@ -2202,7 +2211,9 @@ GLboolean next_ins(r700_AssemblerBase *pAsm) {     struct prog_instruction *pILInst = &(pAsm->pILInst[pAsm->uiCurInst]); -    if( GL_TRUE == IsTex(pILInst->Opcode) )+    if( GL_TRUE == IsTex(pILInst->Opcode) &&+        /* handle const moves to temp register */ +        !(pAsm->D.dst.opcode == SQ_OP2_INST_MOV) )     { 	    if (pILInst->TexSrcTarget == TEXTURE_RECT_INDEX) { 		    if( GL_FALSE == assemble_tex_instruction(pAsm, GL_FALSE) ) @@ -3374,6 +3385,7 @@ GLboolean assemble_TEX(r700_AssemblerBase *pAsm)     case PROGRAM_ENV_PARAM:     case PROGRAM_STATE_VAR:         src_const = GL_TRUE;+        break;     case PROGRAM_TEMPORARY:     case PROGRAM_INPUT:         src_const = GL_FALSE;@@ -3381,8 +3393,9 @@ GLboolean assemble_TEX(r700_AssemblerBase *pAsm)      if (GL_TRUE == src_const)      {-        radeon_error("TODO: Texture coordinates from a constant register not supported.\n");-        return GL_FALSE;+        mov_temp(pAsm, 0);+	//radeon_error("TODO: Texture coordinates from a constant register not supported.\n");+        //return GL_FALSE;     }      switch (pAsm->pILInst[pAsm->uiCurInst].Opcode)