rendered paste bodyIndex: pcsx2/x86/ix86-32/iCore-32.cpp===================================================================--- pcsx2/x86/ix86-32/iCore-32.cpp (revision 930)+++ pcsx2/x86/ix86-32/iCore-32.cpp (working copy)@@ -82,7 +82,7 @@ for (i=0; i<X86REGS; i++) { int reg = (g_x86checknext+i)%X86REGS;- if( reg == 0 || reg == ESP ) continue;+ if( reg == 0 || reg == ESP || reg == EDI ) continue; if( reg >= maxreg ) continue; if( (mode&MODE_NOFRAME) && reg==EBP ) continue; @@ -95,6 +95,7 @@ tempi = -1; for (i=1; i<maxreg; i++) { if( i == ESP ) continue;+ if (i == EDI) continue; if( (mode&MODE_NOFRAME) && i==EBP ) continue; if (x86regs[i].needed) continue;@@ -131,8 +132,13 @@ void _flushConstReg(int reg) { if( GPR_IS_CONST1( reg ) && !(g_cpuFlushedConstReg&(1<<reg)) ) {- MOV32ItoM((int)&cpuRegs.GPR.r[reg].UL[0], g_cpuConstRegs[reg].UL[0]);- MOV32ItoM((int)&cpuRegs.GPR.r[reg].UL[1], g_cpuConstRegs[reg].UL[1]);+ if (reg >= 1 && reg < 17) {+ MOV32ItoRm(EDI, g_cpuConstRegs[reg].UL[0], 16 * (reg - 9));+ MOV32ItoRm(EDI, g_cpuConstRegs[reg].UL[1], 4 + 16 * (reg - 9));+ } else {+ MOV32ItoM((int)&cpuRegs.GPR.r[reg].UL[0], g_cpuConstRegs[reg].UL[0]);+ MOV32ItoM((int)&cpuRegs.GPR.r[reg].UL[1], g_cpuConstRegs[reg].UL[1]);+ } g_cpuFlushedConstReg |= (1<<reg); } }@@ -156,7 +162,10 @@ continue; if (eaxval != 0) XOR32RtoR(EAX, EAX), eaxval = 0;- MOV32RtoM((uptr)&cpuRegs.GPR.r[i].SL[j], EAX);+ if (i >= 1 && i < 17)+ MOV32RtoRm(EDI, EAX, j * 4 + 16 * (i - 9));+ else+ MOV32RtoM((uptr)&cpuRegs.GPR.r[i].SL[j], EAX); done[j] |= 1<<i; zero_cnt++; }@@ -168,11 +177,14 @@ continue; if (g_cpuConstRegs[i].SL[j] != -1) continue;- + if (eaxval > 0) XOR32RtoR(EAX, EAX), eaxval = 0; if (eaxval == 0) NOT32R(EAX), eaxval = -1;- - MOV32RtoM((uptr)&cpuRegs.GPR.r[i].SL[j], EAX);++ if (i >= 1 && i < 17)+ MOV32RtoRm(EDI, EAX, j * 4 + 16 * (i - 9));+ else+ MOV32RtoM((uptr)&cpuRegs.GPR.r[i].SL[j], EAX); done[j + 2] |= 1<<i; minusone_cnt++; }@@ -187,10 +199,19 @@ for (i = 1; i < 32; ++i) { if (GPR_IS_CONST1(i)) { if (!(g_cpuFlushedConstReg&(1<<i))) {- if (!(done[0] & (1<<i)))- MOV32ItoM((uptr)&cpuRegs.GPR.r[i].UL[0], g_cpuConstRegs[i].UL[0]);- if (!(done[1] & (1<<i)))- MOV32ItoM((uptr)&cpuRegs.GPR.r[i].UL[1], g_cpuConstRegs[i].UL[1]);+ if (!(done[0] & (1<<i))) {+ if (i >= 1 && i < 17)+ MOV32ItoRm(EDI, g_cpuConstRegs[i].UL[0], 16 * (i - 9));+ else+ MOV32ItoM((uptr)&cpuRegs.GPR.r[i].UL[0], g_cpuConstRegs[i].UL[0]);+ + }+ if (!(done[1] & (1<<i))) {+ if (i >= 1 && i < 17)+ MOV32ItoRm(EDI, g_cpuConstRegs[i].UL[1], 4 + 16 * (i - 9));+ else+ MOV32ItoM((uptr)&cpuRegs.GPR.r[i].UL[1], g_cpuConstRegs[i].UL[1]);+ } g_cpuFlushedConstReg |= 1<<i; } if (g_cpuHasConstReg == g_cpuFlushedConstReg)@@ -233,6 +254,7 @@ for (i=1; i<maxreg; i++) { if( i == ESP ) continue;+ if (i == EDI) continue; if (!x86regs[i].inuse || x86regs[i].type != type || x86regs[i].reg != reg) continue; @@ -967,9 +989,15 @@ } else { MOVQRtoR(to, from);- MOVDMMXtoM((u32)&cpuRegs.GPR.r[gprreg].UL[0], from);+ if (gprreg >= 1 && gprreg < 17)+ MOVD32MMXtoRm(EDI, from, 16 * (gprreg - 9));+ else+ MOVDMMXtoM((u32)&cpuRegs.GPR.r[gprreg].UL[0], from); PSRADItoR(from, 31);- MOVDMMXtoM((u32)&cpuRegs.GPR.r[gprreg].UL[1], from);+ if (gprreg >= 1 && gprreg < 17)+ MOVD32MMXtoRm(EDI, from, 4 + 16 * (gprreg - 9));+ else+ MOVDMMXtoM((u32)&cpuRegs.GPR.r[gprreg].UL[1], from); mmxregs[to].inuse = 0; return -1; }@@ -1004,21 +1032,36 @@ else { // will be used in the future as mmx if( shift > 0 ) PSRADItoR(to, shift);- MOVDMMXtoM((u32)&cpuRegs.GPR.r[gprreg].UL[0], to);+ if (gprreg >= 1 && gprreg < 17)+ MOVD32MMXtoRm(EDI, to, 16 * (gprreg - 9));+ else+ MOVDMMXtoM((u32)&cpuRegs.GPR.r[gprreg].UL[0], to); PSRADItoR(to, 31);- MOVDMMXtoM((u32)&cpuRegs.GPR.r[gprreg].UL[1], to);+ if (gprreg >= 1 && gprreg < 17)+ MOVD32MMXtoRm(EDI, to, 4 + 16 * (gprreg - 9));+ else+ MOVDMMXtoM((u32)&cpuRegs.GPR.r[gprreg].UL[1], to); // read again- MOVQMtoR(to, (u32)&cpuRegs.GPR.r[gprreg].UL[0]);+ if (gprreg >= 1 && gprreg < 17)+ MOVQRmtoR(to, EDI, 16 * (gprreg - 9));+ else+ MOVQMtoR(to, (u32)&cpuRegs.GPR.r[gprreg].UL[0]); mmxregs[to].mode &= ~MODE_WRITE; return to; } } else { if( shift > 0 ) PSRADItoR(to, shift);- MOVDMMXtoM((u32)&cpuRegs.GPR.r[gprreg].UL[0], to);+ if (gprreg >= 1 && gprreg < 17)+ MOVD32MMXtoRm(EDI, to, 16 * (gprreg - 9));+ else+ MOVDMMXtoM((u32)&cpuRegs.GPR.r[gprreg].UL[0], to); PSRADItoR(to, 31);- MOVDMMXtoM((u32)&cpuRegs.GPR.r[gprreg].UL[1], to);+ if (gprreg >= 1 && gprreg < 17)+ MOVD32MMXtoRm(EDI, to, 4 + 16 * (gprreg - 9));+ else+ MOVDMMXtoM((u32)&cpuRegs.GPR.r[gprreg].UL[1], to); mmxregs[to].inuse = 0; return -1; }Index: pcsx2/x86/ix86-32/iR5900-32.cpp===================================================================--- pcsx2/x86/ix86-32/iR5900-32.cpp (revision 930)+++ pcsx2/x86/ix86-32/iR5900-32.cpp (working copy)@@ -344,7 +344,10 @@ SetMMXstate(); } else {- MOV32MtoR(to, (int)&cpuRegs.GPR.r[ fromgpr ].UL[ 0 ] );+ if (fromgpr >= 1 && fromgpr < 17)+ MOV32RmtoR(to, EDI, 16 * (fromgpr - 9));+ else+ MOV32MtoR(to, (int)&cpuRegs.GPR.r[ fromgpr ].UL[ 0 ] ); } } }@@ -364,7 +367,10 @@ SetMMXstate(); } else {- MOV32MtoR(EAX, (int)&cpuRegs.GPR.r[ fromgpr ].UL[ 0 ] );+ if (fromgpr >= 1 && fromgpr < 17)+ MOV32RmtoR(EAX, EDI, 16 * (fromgpr - 9));+ else+ MOV32MtoR(EAX, (int)&cpuRegs.GPR.r[ fromgpr ].UL[ 0 ] ); MOV32RtoM(to, EAX ); } }@@ -385,7 +391,10 @@ SetMMXstate(); } else {- MOV32MtoR(EAX, (int)&cpuRegs.GPR.r[ fromgpr ].UL[ 0 ] );+ if (fromgpr >= 1 && fromgpr < 17)+ MOV32RmtoR(EAX, EDI, 16 * (fromgpr - 9));+ else+ MOV32MtoR(EAX, (int)&cpuRegs.GPR.r[ fromgpr ].UL[ 0 ] ); MOV32RtoRm( to, EAX ); } }@@ -437,8 +446,13 @@ !_recIsRegWritten(g_pCurInstInfo+1, (s_nEndBlock-pc)/4, XMMTYPE_GPRREG, i) ) { // check if will be written in the future- MOV32ItoM((uptr)&cpuRegs.GPR.r[i].UL[0], g_cpuConstRegs[i].UL[0]);- MOV32ItoM((uptr)&cpuRegs.GPR.r[i].UL[1], g_cpuConstRegs[i].UL[1]);+ if (i >= 1 && i < 17) {+ MOV32ItoRm(EDI, g_cpuConstRegs[i].UL[0], 16 * (i - 9));+ MOV32ItoRm(EDI, g_cpuConstRegs[i].UL[1], 4 + 16 * (i - 9));+ } else {+ MOV32ItoM((uptr)&cpuRegs.GPR.r[i].UL[0], g_cpuConstRegs[i].UL[0]);+ MOV32ItoM((uptr)&cpuRegs.GPR.r[i].UL[1], g_cpuConstRegs[i].UL[1]);+ } g_cpuFlushedConstReg |= 1<<i; return 1; }@@ -696,6 +710,7 @@ push esi push edi push ebp+ mov edi, offset [cpuRegs.GPR.r + 144] call DispatcherReg @@ -718,6 +733,7 @@ push esi push edi push ebp+ mov edi, offset [cpuRegs.GPR.r + 144] call DispatcherReg