rendered paste body
coreboot-2.0.0_m57sli_Fallback Fri Apr 3 17:16:58 EDT 2009 starting...
*sysinfo range: [000cf000,000cf730)
bsp_apicid=00
Enabling routing table for node 00 done.
Enabling UP settings
coherent_ht_finalize
done
core0 started:
started ap apicid: 01
SBLink=00
NC node|link=00
begin msr fid, vid 310a12120a0c0202
Current fid_cur: 0x2, fid_max: 0xc
Requested fid_new: 0xc
FidVid table step fidvid: 0xc
end msr fid, vid 310a120a0a0c020c
entering optimize_link_incoherent_ht
sysinfo->link_pair_num=0x1
entering ht_optimize_link
pos=0x8a, unfiltered freq_cap=0x8075
pos=0x8a, filtered freq_cap=0x75
pos=0x52, unfiltered freq_cap=0x807f
pos=0x52, filtered freq_cap=0x7f
freq_cap1=0x75, freq_cap2=0x7f
dev1 old_freq=0x0, freq=0x6, needs_reset=0x1
dev2 old_freq=0x0, freq=0x6, needs_reset=0x1
width_cap1=0x11, width_cap2=0x11
dev1 input ln_width1=0x4, ln_width2=0x4
dev1 input width=0x1
dev1 output ln_width1=0x4, ln_width2=0x4
dev1 input|output width=0x11
old dev1 input|output width=0x11
dev2 input|output width=0x11
old dev2 input|output width=0x11
after ht_optimize_link for link pair 0, reset_needed=0x1
after optimize_link_read_pointers_chain, reset_needed=0x1
mcp55_num:01
ht reset -
coreboot-2.0.0_m57sli_Fallback Fri Apr 3 17:16:58 EDT 2009 starting...
*sysinfo range: [000cf000,000cf730)
bsp_apicid=00
Enabling routing table for node 00 done.
Enabling UP settings
coherent_ht_finalize
done
core0 started:
started ap apicid: 01
SBLink=00
NC node|link=00
begin msr fid, vid 310a120a0a0c020c
end msr fid, vid 310a120a0a0c020c
entering optimize_link_incoherent_ht
sysinfo->link_pair_num=0x1
entering ht_optimize_link
pos=0x8a, unfiltered freq_cap=0x8075
pos=0x8a, filtered freq_cap=0x75
pos=0x52, unfiltered freq_cap=0x7f
pos=0x52, filtered freq_cap=0x7f
freq_cap1=0x75, freq_cap2=0x7f
dev1 old_freq=0x6, freq=0x6, needs_reset=0x0
dev2 old_freq=0x6, freq=0x6, needs_reset=0x0
width_cap1=0x11, width_cap2=0x11
dev1 input ln_width1=0x4, ln_width2=0x4
dev1 input width=0x1
dev1 output ln_width1=0x4, ln_width2=0x4
dev1 input|output width=0x11
old dev1 input|output width=0x11
dev2 input|output width=0x11
old dev2 input|output width=0x11
after ht_optimize_link for link pair 0, reset_needed=0x0
after optimize_link_read_pointers_chain, reset_needed=0x0
mcp55_num:01
Ram1.00
setting up CPU 00 northbridge registers
done.
Ram2.00
sdram_set_spd_registers: paramx :000cee30
DIMM socket 0, channel 0 SPD device is 0x50
DIMM socket 0, channel 1 SPD device is 0x51
DIMM socket 1, channel 0 SPD device is 0x52
DIMM socket 1, channel 1 SPD device is 0x53
DIMM socket 2, channel 0 SPD device is 0x00
DIMM socket 2, channel 1 SPD device is 0x00
DIMM socket 3, channel 0 SPD device is 0x00
DIMM socket 3, channel 1 SPD device is 0x00
sdram_set_spd_registers: dimm_mask=0x11
Common CAS latency bitfield: 0x70
Enabling dual channel memory
spd_enable_2channels: dimm_mask=0x11
spd_set_ram_size: dimm_mask=0x11
Unbuffered
spd_handle_unbuffered_dimms: dimm_mask=0x11
1 min_cycle_time: 00000250
1.1 dimm_mask: 00000011
i: 00000000
Channel 0 settings:
latencies: 00000070
index: 00000000
latency: 00000004
value1: 0000003d
value2: 00000375
new_cycle_time: 00000375
new_latency: 00000004
index: 00000001
latency: 00000005
value1: 00000030
value2: 00000300
new_cycle_time: 00000300
new_latency: 00000005
index: 00000002
latency: 00000006
value1: 00000025
value2: 00000250
new_cycle_time: 00000250
new_latency: 00000006
2 min_cycle_time: 00000250
2 min_latency: 00000006
Channel 1 settings:
latencies: 00000070
index: 00000000
latency: 00000004
value1: 0000003d
value2: 00000375
new_cycle_time: 00000375
new_latency: 00000004
index: 00000001
latency: 00000005
value1: 00000030
value2: 00000300
new_cycle_time: 00000300
new_latency: 00000005
index: 00000002
latency: 00000006
value1: 00000025
value2: 00000250
new_cycle_time: 00000250
new_latency: 00000006
2 min_cycle_time: 00000250
2 min_latency: 00000006
1.1 dimm_mask: 00000011
i: 00000001
1.1 dimm_mask: 00000011
i: 00000002
1.1 dimm_mask: 00000011
i: 00000003
3 min_cycle_time: 00000250
3 min_latency: 00000006
4 min_cycle_time: 00000250
400MHz
400MHz
spd_set_memclk: dimm_mask=0x11
spd_set_dram_timing dimm socket: 00000000
trc
update_dimm_Trc: tRC (41) = 0000003c
update_dimm_Trc: tRC final value = 2400
update_dimm_Trc: clocks = 24
update_dimm_Trc: clocks after adjustment = 24
trcd
trrd
tras
update_dimm_Tras: 0 value= 0000002d
update_dimm_Tras: 1 value= 00000708
update_dimm_Tras: divisor= 00000064
update_dimm_Tras: clocks= 00000012
trp
trtp
twr
tref
twtr
spd_set_dram_timing dimm_err!
disabling dimm 00
set_ecc spd_device: 0x51
spd_set_dram_timing: dimm_mask=0x10
No memory?