Mine

wb_init( bus_c);        -- initalise wishbone bus
wb_rst( 2, reset_int, bus_c ); -- reset system for 2 clocks
clock_wait( 2, bus_c );

bka_test_array(0) := X"0000_0003";	-- LCR
bkd_test_array(0) := X"0000_0083";	-- 8 data bits, 1 start bit, set LCR(7)  
bkw_32( bka_test_array, bkd_test_array, 1, bus_c);
clock_wait( 2, bus_c );

bka_test_array(0) := X"0000_0001";	-- DLM 
bkd_test_array(0) := X"0000_0000";	-- X"0000_0000" = BAUD 38400 
bkw_32( bka_test_array, bkd_test_array, 1, bus_c);
clock_wait( 2, bus_c );

bka_test_array(0) := X"0000_0000";	-- DLL 
bkd_test_array(0) := X"0000_0005";	-- X"0000_0051" = BAUD 38400  
bkw_32( bka_test_array, bkd_test_array, 1, bus_c);
clock_wait( 2, bus_c );

bka_test_array(0) := X"0000_0003";	-- LCR
bkd_test_array(0) := X"0000_0003";	-- 8 data bits, 1 start bit, clear LCR(7)  
bkw_32( bka_test_array, bkd_test_array, 1, bus_c);
clock_wait( 2, bus_c );

bka_test_array(0) := X"0000_0000";	-- Transmiter fifo
bkd_test_array(0) := X"0000_0003";	-- data  
bkw_32( bka_test_array, bkd_test_array, 1, bus_c);
clock_wait( 2, bus_c );

bka_test_array(0) := X"0000_0000";	-- Transmiter fifo
bkd_test_array(0) := X"0000_0005";	-- data  
bkw_32( bka_test_array, bkd_test_array, 1, bus_c);
clock_wait( 2, bus_c );

clock_wait( 5000, bus_c );

bka_test_array(0) := X"0000_0000";	-- Transmiter fifo
bkd_test_array(0) := X"0000_0003";	-- data  
bkw_32( bka_test_array, bkd_test_array, 1, bus_c);
clock_wait( 2, bus_c );

clock_wait( 5000, bus_c );

bka_test_array(0) := X"0000_0000";	-- Transmiter fifo
bkd_test_array(0) := X"0000_0005";	-- data  
bkw_32( bka_test_array, bkd_test_array, 1, bus_c);
clock_wait( 2, bus_c );

clock_wait( 5000, bus_c );

bka_test_array(0) := X"0000_0000";	-- Transmiter fifo
bkd_test_array(0) := X"0000_0033";	-- data  
bkw_32( bka_test_array, bkd_test_array, 1, bus_c);
clock_wait( 2, bus_c );

bka_test_array(0) := X"0000_0000";	-- Transmiter fifo
bkd_test_array(0) := X"0000_0055";	-- data  
bkw_32( bka_test_array, bkd_test_array, 1, bus_c);
clock_wait( 2, bus_c );

clock_wait( 5000, bus_c );

bka_test_array(0) := X"0000_0000";	-- Transmiter fifo
bkd_test_array(0) := X"0000_0033";	-- data  
bkw_32( bka_test_array, bkd_test_array, 1, bus_c);
clock_wait( 2, bus_c );

clock_wait( 5000, bus_c );

bka_test_array(0) := X"0000_0000";	-- Transmiter fifo
bkd_test_array(0) := X"0000_0055";	-- data  
bkw_32( bka_test_array, bkd_test_array, 1, bus_c);
clock_wait( 2, bus_c );