Mine

Index: raminit.c
===================================================================
--- raminit.c	(Revision 3755)
+++ raminit.c	(Arbeitskopie)
@@ -22,6 +22,7 @@
 #include <spd.h>
 #include <sdram_mode.h>
 #include <delay.h>
+#include "lib/debug.c"
 #include "i82810.h"
 
 /*-----------------------------------------------------------------------------
@@ -29,7 +30,7 @@
 -----------------------------------------------------------------------------*/
 
 /* Uncomment this to enable debugging output. */
-// #define DEBUG_RAM_SETUP 1
+#define DEBUG_RAM_SETUP 1
 
 /* Debugging macros. */
 #if defined(DEBUG_RAM_SETUP)
@@ -55,6 +56,21 @@
 #define RAM_COMMAND_MRS		 0x6
 #define RAM_COMMAND_CBR		 0x7
 
+/* Table which returns the RAM size in MB when fed the DRP[7:4] or [3:0] value.
+ * Note that 2 is a value which the DRP should never be programmed to.
+ * Some size values appear twice, due to single-sided vs dual-sided banks.
+ */
+static const u16 translate_i82810_to_mb[] = {
+/* DRP	0  1 (2) 3   4   5   6   7   8   9   A   B   C    D    E    F */
+/* MB */0, 8, 0, 16, 16, 24, 32, 32, 48, 64, 64, 96, 128, 128, 192, 256,
+};
+
+/* size of bank#0 for dual-sided DIMMs */
+static const u16 translate_i82810_to_bank[] = {
+/* DRP	0  1 (2) 3  4  5   6   7  8   9   A  B   C   D  E    F */
+/* MB */0, 0, 0, 8, 0, 16, 16, 0, 32, 32, 0, 64, 64, 0, 128, 128,
+};
+
 /*-----------------------------------------------------------------------------
 SDRAM configuration functions.
 -----------------------------------------------------------------------------*/
@@ -69,10 +85,10 @@
 static void do_ram_command(const struct mem_controller *ctrl, uint32_t command,
 			   uint32_t addr_offset, uint32_t row_offset)
 {
-	uint8_t reg;
+	u16 dimm_size, dimm_start, dimm_bank;
+	u8 reg, drp;
+	int i;
 
-	/* TODO: Support for multiple DIMMs. */
-
 	/* Configure the RAM command. */
 	reg = pci_read_config8(ctrl->d0, DRAMT);
 	reg &= 0x1f;		/* Clear bits 7-5. */
@@ -83,15 +99,32 @@
 	   doesn't need to be "sent" to the DIMMs. */
 	/* if (command == RAM_COMMAND_NORMAL) return; */
 
-	PRINT_DEBUG("    Sending RAM command 0x");
-	PRINT_DEBUG_HEX8(reg);
-	PRINT_DEBUG(" to 0x");
-	PRINT_DEBUG_HEX32(0 + addr_offset);	// FIXME
-	PRINT_DEBUG("\r\n");
+	dimm_start = 0;
 
-	/* Read from (DIMM start address + addr_offset). */
-	read32(0 + addr_offset);	//first offset is always 0
-	read32(row_offset + addr_offset);
+	for (i = 0; i < DIMM_SOCKETS ; i++) {
+		drp = pci_read_config8(ctrl->d0, DRP);
+		drp = (drp >> (i * 4)) & 0x0f;
+
+		dimm_size = translate_i82810_to_mb[drp];
+		if (dimm_size) {
+			PRINT_DEBUG("    Sending RAM command 0x");
+			PRINT_DEBUG_HEX8(reg);
+			PRINT_DEBUG(" to 0x");
+			PRINT_DEBUG_HEX32((dimm_start * 1024 * 1024) + addr_offset);
+			PRINT_DEBUG("\r\n");
+			read32((dimm_start * 1024 * 1024) + addr_offset);
+		}
+
+		dimm_bank = translate_i82810_to_bank[drp];
+		if (dimm_bank) {
+			read32(((dimm_start + dimm_bank) 
+				* 1024 * 1024) + addr_offset);
+		}
+
+		dimm_start += dimm_size;
+	}
+	/* TODO */
+	//read32((dimm_start * 4 * 1024 * 1024) + addr_offset);
 }
 
 /*-----------------------------------------------------------------------------